Rakefet Kol

A doubly-latched asynchronous pipeline

DLAP, an asynchronous pipeline with master-slave (dual) registers, offers improved performance. It is most suitable for converting synchronous circuits into asynchronous ones. DLAP is capable of truly decoupled operation: All pipeline stages can shift data simultaneously, and execution is faster than previous designs when variable delays are encountered. Implementations based on both edge triggered registers and transparent latches are shown. STG and verified controllers are presented and simulated.

Asynchronous design by conversion: converting synchronous circuits into asynchronous ones

A novel methodology and algorithm for the design of large low-power asynchronous systems are described. The system is synthesized by a commercial tool as a synchronous circuit, and subsequently converted into an asynchronous one. The conversion algorithm consists of extracting input and output sets, replacing the storage elements, identifying fork and join sets, and constructing request and acknowledge networks. A DLAP (doubly latched asynchronous pipeline) architecture is employed. The resulting asynchronous circuit can adapt its effective operating frequency to the supply voltage, facilitating flexible and efficient power management. The algorithm has been validated on several circuits.

Average-case optimized technology mapping of one-hot domino circuits

This paper presents a technology mapping technique for optimizing the average-case delay of asynchronous combinational circuits implemented using domino logic and one-hot encoded outputs. The technique minimizes the critical path for common input patterns at the possible expense of making less common critical paths longer. To demonstrate the application of this technique, we present a case study of a combinational length decoding block, an integral component of an Asynchronous Instruction Length Decoder (AILD) which can be used in Pentium(R) processors. The experimental results demonstrate that the average-case delay of our mapped circuits can be dramatically lower than the worst-case delay of the circuits obtained using conventional worst-case mapping techniques.

Kin : a high performance asynchronous processor architecture

rakefet@tx.technion.ac.il Kin is an asynchronous processor architecture designed for future technologies enabling one or more billion transistors per chip and extremely fast processing (e.g., as predicted for 2012). This huge resource is exploited for aggressive avid execution, where a large number of instructions (hundreds per cycle) are prefetched and executed speculatively, in order to reduce the penalty of stalls due to branch mispredictions and dependencies, and to yield a very aggressive rate of successfully completed instructions (tens of instructions every cycle). Unneeded instructions are removed efficiently and nonpreemptively, under control of apruning mechanism. A multi-ported, wide bandwidth decoded instruction cache, wherein each line is a program basic block, is employed to feed this voracious machine, and a multi-path prcfetch unit generates multiple cache accesses each cycle. Instructions are fully identified with Dynamic Instance Tags and move about the processor as independent entities. Kin supports multiexecution, where multiple paths, threads and processes are all executed simultaneously out of order. The processor has been designed using statecharts, and has been simulated running the SpecInt95 benchmark. We conclude that such complexity, which seems necessary for very high performance computing, is best achieved with an asynchronous architecture.

Statechart methodology for the design, validation, and synthesis of large scale asynchronous systems

We apply a novel methodology, based on statecharts, for the design of large scale asynchronous systems. The EXV CAD tool offers specification at multiple levels, simulation, animation, and compilation into synthesizable VHDL code. EXV has some verification capabilities, and we add a validation sub-system EXV is originally synchronous, but we discuss how to employ it for asynchronous design. The tool is demonstrated through a simple FSM.