Michael Yoeli

An efficient implementation of Boolean functions as self-timed circuits

The authors propose a general synthesis method for efficiently implementing any family of Boolean functions over a set of variables, as a self-timed logic module. Interval temporal logic is used to express the constraints that are formulated for the self-timed logic module. A method is provided for proving the correct behavior of the designed circuit, by showing that it obeys all the functional constraints. The resulting circuit is compared with alternative proposed self-timed methodologies. This approach is shown to require less gates than other methods. The proposed method is appropriate for automatic synthesis of self-timed systems. A formal proof of correctness is provided. >

Application of Ternary Algebra to the Study of Static Hazards

This paper is concerned with the study of static hazards in combinational switching circuits by means of a suitable ternary switching algebra. Techniques for hazard detection and elimination are developed which are analogous to the Huffman-McCluskey procedures. However, gate and series-parallel contact networks are treated by algebraic methods exclusively, whereas a topological approach is applied to non-series-parallel contact networks only. Moreover, the paper derives necessary and sufficient conditions for a ternary function to adequately describe the steady-state and static hazard behavior of a combinational network. The sufficiency of these conditions is proved constructively leading to a method for the synthesis of combinational networks containing static hazards as specified. The section on non-series-parallel contact networks also includes a brief discussion of the applicability of lattice matrix theory to hazard detection. Finally, hazard prevention in contact networks by suitable contact sequencing techniques is discussed and a ternary map method for the synthesis of such networks is explained.

Logical Design of Ternary Switching Circuits

A logical design theory for ternary voltage switching circuits is developed. The theory is based on familiar binary switching circuit elements and simplification methods. The theory thus leads to simple electronic realization. The basic system of ternary switching elements consists of function realizable by means of either diode gates or a single triode (transistor). Various simplification methods for combinational circuits are described, namely a map method and two algebraic methods. The first algebraic method is an adaptation of the Quine method for determining the prime implicants of a given binary function, and the second is a modification of the Scheinman binary method.

Self-timed is self-checking

Self-checking circuits detect (at least some of) their own faults. We describe self-timed circuits, including combinational logic and sequential machines, which either halt or generate illegal output if they include any single stuck-at faults. The self-timed circuits employ dual rail data encoding to implement ternary logic of 0, 1, andundefined states; the fourth state is used to signal illegal output and is shown to result only from certain circuit faults. The self-timed circuits also employ four-phase signaling according to a well-defined protocol of communications between the circuit and its environment; failures due to certain faults prevent the circuit from communicating properly, thus causing the circuit to halt. We show that any single stuck-at fault falls in either the first or the second category, thus providing complete fault coverage through self checking. No hardware needs to be added to our circuits to achieve the complete self-checking property; further, the circuit is guaranteed to never generate a legal but erroneous output if it contains a fault. Minimal hardware is needed to detect that a circuit has either halted or has generated an illegal output.

The Cascade Decomposition of Sequential Machines

This paper studies composite sequential machines obtained from smaller component machines by their connection in cascade, that is, the outputs from one component are the inputs to the next. Given the specification of a deterministic, completely specified, synchronous, sequential machine (Mealy model), a criterion is derived for such a specification to be decomposable into specifications of smaller machines, the cascading of which will lead to a realization of the original machine required. A simple technique, based on homomorphisms between directed graphs, is arrived at for the actual breaking up of a decomposable specification. A number of additional problems related to sequential machine decompositions are pointed out as concluding remarks.

Vector addition systems and regular languages

Abstract Necessary and sufficient conditions are established for Vector Addition Systems to define regular languages. An algorithm is designed to decide whether these conditions are satisfied. The reachability problem for such Vector Addition Systems is shown to be decidable.

Implementing sequential machines as self-timed circuits

A self-timed finite state machine (FSM) is described. It is based on a formally proven, efficient implementation of self-timed combinational logic and a self-timed master-slave register. Temporal behavioral constraints are formalized, and the system is shown to abide by them. The synthesis method is algorithmic and serves as an automatic compiler of self-timed FSMs. The specification of the FSM is given by a state table, similar to that of synchronous machines. The circuit operates according to a sequence of events that replaces the role of the central clock in the synchronous FSM. The inputs and outputs of the circuit are double-rail (or ternary) and the circuit produces a completion signal. The method is compared with other approaches. >

A Group-Theoretical Approach to Two-Rail Cascades

A two-rail cascade is a one-dimensional binary logic cellular array wherein each noninitial cell has two inputs from the preceding cell and one external input. The initial cell has three external inputs, and the last cell one or two external outputs. The interest in two-rail cascades is due to the fact that one-output two-rail cascades are known to be functionally complete. This paper is concerned with two-output two-rail cascades and derives new synthesis procedures for four and five input variables. These procedures utilize certain properties of the symmetric group of degree 4, as well as known functional decomposition techniques.

Products of automata and the problem of covering

Abstract : Convenient relational techniques for the description and study of complete or partial, finite or infinite automata is introduced. By associating with every input two binary relations an easy and concise algebraic method for the study of homomorphisms and covering of automata is obtained. (Author)

On homomorphic images of transition graphs

Abstract A simple method is derived for obtaining all homomorphic images of a transition graph, i.e., a finite, directed graph with at most one edge issuing from each vertex. The method consists of the successive application of elementary steps, corresponding to four types of “elementary” congruences. It is also shown that the number of elementary steps required to derive a given homomorphic image is constant, if the original transition graph is complete and connected. The applicability of this study to sequential machine decompositions is outlined.