Ran Ginosar

QNoC: QoS architecture and design process for network on chip

We define Quality of Service (QoS) and cost model for communications in Systems on Chip (SoC), and derive related Network on Chip (NoC) architecture and design process. SoC inter-module communication traffic is classified into four classes of service: signaling (for inter-module control signals); real-time (representing delay-constrained bit streams); RD/WR (modeling short data access) and block-transfer (handling large data bursts). Communication traffic of the target SoC is analyzed (by means of analytic calculations and simulations), and QoS requirements (delay and throughput) for each service class are derived. A customized Quality-of-Service NoC (QNoC) architecture is derived by modifying a generic network architecture. The customization process minimizes the network cost (in area and power) while maintaining the required QoS.The generic network is based on a two-dimensional planar mesh and fixed shortest path (X-Y based) multiclass wormhole routing. Once communication requirements of the target SoC are identified, the network is customized as follows: The SoC modules are placed so as to minimize spatial traffic density, unnecessary mesh links and switching nodes are removed, and bandwidth is allocated to the remaining links and switches according to their relative load so that link utilization is balanced. The result is a low cost customized QNoC for the target SoC which guarantees that QoS requirements are met.

A random access photodiode array for intelligent image capture

A chip implementing random scan was designed, fabricated, and tested. The chip covers the basic requirements for random access and separation between the sampling and reading processes. In this way, a repeated reading of any pixel at any time can take place. The chip includes an 80*80 matrix of basic cells. Each cell consists of two stages: The first is based on a switch, whereas the second includes a buffer. The chip was fabricated in a 3- mu m CMOS process. It was found to operate functionally. However, the use of a standard process gave rise to the crosstalk phenomenon, which has yet to be overcome. >

An efficient implementation of Boolean functions as self-timed circuits

The authors propose a general synthesis method for efficiently implementing any family of Boolean functions over a set of variables, as a self-timed logic module. Interval temporal logic is used to express the constraints that are formulated for the self-timed logic module. A method is provided for proving the correct behavior of the designed circuit, by showing that it obeys all the functional constraints. The resulting circuit is compared with alternative proposed self-timed methodologies. This approach is shown to require less gates than other methods. The proposed method is appropriate for automatic synthesis of self-timed systems. A formal proof of correctness is provided. >

An Integrated System for Multichannel Neuronal Recording With Spike/LFP Separation, Integrated A/D Conversion and Threshold Detection

A mixed-signal front-end processor for multichannel neuronal recording is described. It receives 12 differential-input channels of implanted recording electrodes. A programmable cutoff High Pass Filter (HPF) blocks dc and low-frequency input drift at about 1 Hz. The signals are band-split at about 200 Hz to low-frequency Local Field Potential (LFP) and high-frequency spike data (SPK), which is band limited by a programmable-cutoff LPF, in a range of 8-13 kHz. Amplifier offsets are compensated by 5-bit calibration digital-to-analog converters (DACs). The SPK and LFP channels provide variable amplification rates of up to 5000 and 500, respectively. The analog signals are converted into 10-bit digital form, and streamed out over a serial digital bus at up to 8 Mbps. A threshold filter suppresses inactive portions of the signal and emits only spike segments of programmable length. A prototype has been fabricated on a 0.35-mum CMOS process and tested successfully, demonstrating a 3-muV noise level. Special interface system incorporating an embedded CPU core in a programmable logic device accompanied by real-time software has been developed to allow connectivity to a computer host

Data synchronization issues in GALS SoCs

Locally generated, arbitrated clocks for GALS SoCs as stated in S. Moore et al. (April 2002) face the risk of synchronization failures if clock delays are not accounted for. The problem is analyzed based on clock delays, cycle times, and complexity of the asynchronous port controllers. A number of methods are presented. In some cases, it is sufficient to extract all the delays and verify whether the system is susceptible to metastability. In other cases, when high data bandwidth is not required, asynchronous synchronizers or matched-delay asynchronous ports may be employed. Arbitrated clocks may be traded off for locally delayed input and output ports, facilitating high data rates. The latter circuits have been simulated, to verify their performance.

An asynchronous router for multiple service levels networks on chip

Networks on chip that can guarantee quality of service (QNoC) are based on special routers that can support multiple service levels. GALS SoCs call for asynchronous NoC implementations, to eliminate the need for synchronization when crossing clock domains. An asynchronous multi-service level QNoC router is investigated. It comprises multiple interconnected input and output ports, and arbitration mechanisms that resolve any output port and service level conflicts. Buffering and credit based transport are enabled, enhancing throughput. A synchronous and an asynchronous router have been designed, and their performance is compared. The asynchronous router requires less area and enables a higher data rate.

Cost considerations in network on chip

Systems on Chip (SoCs) require efficient inter-module interconnection providing for the required communications at a low cost. We analyze the generic cost in area and power of Networks on Chip (NoCs) and alternative interconnect architectures: a shared bus, a segmented bus and a point-to-point interconnect. For each architecture we derive analytical expressions for area, power dissipation and operating frequency as well as asymptotic limits of these functions. The analysis quantifies the intuitive NoC scalability advantages.Next we turn to NoC cost optimization. We explore cost tradeoffs between the number of buffers and the link speed. We use a reference architecture, termed QNoC (Quality-of-Service NoC), which is based on a grid of wormhole switches, shortest path routing and multiple QoS classes. Two traffic scenarios are considered, one dominated by short packets sensitive to queuing delays and the other dominated by large block-transfers. Our simulations show that network cost can be minimized while maintaining quality of service, by trading off buffers with links in the first scenario but not in the second.

Metastability and Synchronizers: A Tutorial

Metastability can arise whenever a signal is sampled close to a transition, leading to indecision as to its correct value. Synchronizer circuits, which guard against metastability, are becoming ubiquitous with the proliferation of timing domains on a chip. Despite the critical importance of reliable synchronization, this topic remains inadequately understood. This tutorial provides a glimpse into the theory and practice of this fascinating subject.

The Power of Priority: NoC Based Distributed Cache Coherency

The paper introduces network-on-chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance chip multi processors (CMPs). We address previously proposed CMP architectures based on non uniform cache architecture (NUCA) over NoC, analyze basic memory transactions and translate them into a set of network transactions. We first show how a simple, generic NoC which is equipped with needed module interface functionalities can provide infrastructure for the coherent access of both static and dynamic NUCA. Then we show how several low cost mechanisms incorporated into such a vanilla NoC can facilitate CMP and boost performance of a cache coherent NUCA CMP. The basic mechanism is based on priority support embedded in the NoC, which differentiates between short control signals and long data messages to achieve a major reduction in cache access delay. The low cost priority-based NoC is extremely useful for increasing performance of almost any other CMP transaction. Priority-based NoC along with the discussed NoC interfaces are evaluated in detail using CMP-NoC simulations across several SPLASH-2 benchmarks and static Web content serving benchmarks showing substantial L2 cache access delay reduction and overall program speedup

Timing measurements of synchronization circuits

A regular (two-flop) synchronizer and six multi-synchronous synchronizers are implemented on a programmable logic device and are measured. An experimental system and method for measuring synchronizers and metastable flip-flops are described. Two separate settling time constants are shown for a metastable flop, confirming earlier results of Dike and Burton [1999]. Clocking cross-talk between asynchronous clocks is demonstrated. The regular synchronizer is useful for communications between asynchronous clock domains, while the other synchronizers can provide higher bandwidth communications between multi-synchronous and mesochronous domains.