Chi-Weon Yoon

A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology

The market growth of mobile applications such as smart phones and tablet computers has fueled the explosive demand of NAND Flash memories having high density and fast throughput. To meet such a demand, we present a 64Gb multilevel cell (MLC) NAND Flash memory having 533Mb/s DDR interface in sub-20nm technology. Large floating-gate (FG) coupling interference and program disturbance are major challenges to impede the scaling of NAND Flash memories in sub-20nm technology node [1]. In this paper, we present correction-before-coupling (CBC) reprogram and P3-pattern pre-pulse scheme, allowing us to overcome large FG coupling interferences. We improve program disturbance by inventing inhibit-channel-coupling-reduction (ICCR) technique. In addition, we achieve a 533Mb/s DDR interface by employing a wave-pipeline architecture [2].

Disturbance-suppressed ReRAM write algorithm for high-capacity and high-performance memory

In this paper, the mechanism of write disturbance, a unique phenomenon in high density ReRAM, is experimentally identified and quantified using fabricated test array. Based on the analysis, disturbance-suppressed ReRAM write algorithm is proposed to prove the feasibility of future high-capacity and high-performance ReRAM memory for NAND applications. By appropriately controlling WL and BL bias, surge current that causes write disturbance is successfully suppressed so that the overall cell distribution was narrowed down by more than 70%.