Ramin Ghodsi

A 3bit/cell 32Gb NAND flash memory at 34nm with 6MB/s program throughput and with dynamic 2b/cell blocks configuration mode for a program throughput increase up to 13MB/s

In recent years applications such as mp3 players, SSD, digital cameras and video camcorders have driven the development of increasingly higher density NAND memories. In the presented 3b/cell memory the read and programming throughputs are been enhanced with the adoption of a quad-plane architecture and an industry standard even-odd bitline (BL) decoding scheme. The architecture, while featuring same page size of 16KB as recently disclosed ABL architectures [3,4], avoids the shortcomings such an ABL scheme exhibits in programming mode due to floating-gate-to-floating-gate coupling. The chip features both the newly developed synchronous DDR interface and the standard, asynchronous NAND flash interface. A 66-cell string is adopted to optimize the die size at 126mm2.

19.1 A 128Gb MLC NAND-Flash device using 16nm planar cell

The aggressive scaling of NAND Flash memory technology - one that is even outpacing Moores Law - has enabled very rapid cost-per-bit reduction, resulting in an explosion of systems utilizing this versatile memory technology. From removable media and personal music players to smart phones, tablets, and now personal computers and data center applications employing client and enterprise solid state drives (SSDs), NAND technology is making solid-state memory-based storage affordable.

7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory

A planar floating-gate NAND technology has previously realized a 0.87Gb/mm2 memory density using 3b/cell [1] and achieved a minimum feature size for 16nm [2]. However, the development of planar NAND flash is expected to reach the scaling limit in a few technology generations. To break though this limit, a significant shift to 3D NAND flash has begun and several types of 3D memory cell structures have been proposed and discussed [3-5]. Recently a 3D V-NAND technology achieved 1.86Gb/mm2 using charge-trap cells and 3b/cell [6]. This paper presents a 3b/cell NAND flash memory utilizing a 3D floating gate (FG) technology that achieves 4.29Gb/mm2.

A 128Gb 3b/cell NAND flash design using 20nm planar-cell technology

The authors develop a 128Gb 3b/cell NAND Flash memory based on 20nm fully planar cell process technology. The planar cell allows the memory cell to be scaled in both the wordline (WL) and bitline (BL) directions, resulting in a small 3b/cell memory device. The sensing scheme is based on a ramping technique that allows the detection of hard and soft states in a single operation.

Effects of Source Diffusion on SILC and Cycling-Induced Charge Loss in Source-Bias Erase Flash Cells

A recent report reveals that in source-bias erase flash cells, light source doping can cause room temperature erratic charge loss after program/erase cycling. In this paper, we present tunnel oxide hole trapping and stress induced leakage current (SILC) measurements under source-bias erase stress conditions, in cell structures with different source doping profiles. Data suggests the deep depletion in cell source during erase causes hole trapping in tunnel oxide above the source diffusion, which is responsible for the room temperature charge loss after P/E cycling for light doping source