Mark A. Helm
Micron Technology
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Publication
Featured researches published by Mark A. Helm.
international solid-state circuits conference | 2014
Mark A. Helm; Jae-Kwan Park; Ali Ghalam; Jason Guo; Chang wan Ha; Cairong Hu; Heonwook Kim; Kalyan Kavalipurapu; Eric N. Lee; Ali Mohammadzadeh; Dan Nguyen; Vipul Patel; Ted Pekny; Bill Saiki; Daesik Song; Jeff Tsai; Vimon Viajedor; Luyen Vu; Tin-Wai Wong; Jung Hee Yun; Ramin Ghodsi; Andrea D'Alessandro; Domenico Di Cicco; Violante Moschiano
The aggressive scaling of NAND Flash memory technology - one that is even outpacing Moores Law - has enabled very rapid cost-per-bit reduction, resulting in an explosion of systems utilizing this versatile memory technology. From removable media and personal music players to smart phones, tablets, and now personal computers and data center applications employing client and enterprise solid state drives (SSDs), NAND technology is making solid-state memory-based storage affordable.
international solid-state circuits conference | 2016
Tomoharu Tanaka; Mark A. Helm; Tommaso Vali; Ramin Ghodsi; Koichi Kawai; Jae-Kwan Park; Shigekazu Yamada; Feng Pan; Yuichi Einaga; Ali Ghalam; Toru Tanzawa; Jason Guo; Takaaki Ichikawa; Erwin Yu; Satoru Tamada; Tetsuji Manabe; Jiro Kishimoto; Yoko Oikawa; Yasuhiro Takashima; Hidehiko Kuge; Midori Morooka; Ali Mohammadzadeh; Jong Kang; Jeff Tsai; Emanuele Sirizotti; Eric N. Lee; Luyen Vu; Yuxing Liu; Hoon Choi; Kwonsu Cheon
A planar floating-gate NAND technology has previously realized a 0.87Gb/mm2 memory density using 3b/cell [1] and achieved a minimum feature size for 16nm [2]. However, the development of planar NAND flash is expected to reach the scaling limit in a few technology generations. To break though this limit, a significant shift to 3D NAND flash has begun and several types of 3D memory cell structures have been proposed and discussed [3-5]. Recently a 3D V-NAND technology achieved 1.86Gb/mm2 using charge-trap cells and 3b/cell [6]. This paper presents a 3b/cell NAND flash memory utilizing a 3D floating gate (FG) technology that achieves 4.29Gb/mm2.
international solid-state circuits conference | 2013
Giovanni Naso; L. Botticchio; M. Castelli; C. Cerafogli; M. Cichocki; P. Conenna; Andrea D'Alessandro; Luca De Santis; Domenico Di Cicco; W. D. Francesco; M. L. Gallese; Girolamo Gallo; Michele Incarnati; C. Lattaro; Agostino Macerola; Giulio Marotta; Violante Moschiano; D. Orlandi; F. Paolini; S. Perugini; Luigi Pilolli; P. Pistilli; G. Rizzo; F. Rori; Massimo Rossini; Giovanni Santin; E. Sirizotti; A. Smaniotto; U. Siciliani; Marco-Domenico Tiburzi
The authors develop a 128Gb 3b/cell NAND Flash memory based on 20nm fully planar cell process technology. The planar cell allows the memory cell to be scaled in both the wordline (WL) and bitline (BL) directions, resulting in a small 3b/cell memory device. The sensing scheme is based on a ramping technique that allows the detection of hard and soft states in a single operation.
Archive | 1995
Mark A. Helm; Charles H. Dennison
Archive | 2007
Mark A. Helm; Xianfeng Zhou
Archive | 1995
Charles H. Dennison; Mark A. Helm
Archive | 1999
Charles H. Dennison; Mark A. Helm
Archive | 2014
Uday Chandrasekhar; Mark A. Helm
Archive | 2013
Matthew Goldman; Pranav Kalavade; Uday Chandrasekhar; Mark A. Helm
Archive | 2005
Mark A. Helm; Roger W. Lindsay
