Ramin Hojati

Heuristic Minimization of BDDs Using Don't Cares

We present heuristic algorithms for finding a minimum BDD size cover of an incompletely specified function, assuming the variable ordering is fixed. In some algorithms based on BDDs, incompletely specified functions arise forwhich any cover of the functionwill suffice. Choosing a cover that has a small BDD representation may yield significant performance gains. We present a systematic study of this problem, establishing a unified framework for heuristic algorithms, proving optimality in some cases,and presenting experimental results.

Early quantification and partitioned transition relations

Hardware systems are generally specified as a set of interacting finite state machines (FSMs). An important problem in formal verification using Binary Decision Diagrams (BDDs) is forming the transition relation of the product machine. This problem reduces to conjuncting (or multiplying) the BDDs representing the transition relations of the individual machines, and then existentially quantifying out the set of input and output variables. The resulting graph is called the product graph. Computing the set of reachable states of the product graph is the central verification problem. In this paper, we discuss two related problems. The early quantification problem is the problem of interleaving multiplication of a set of BDDs with the quantification of a set of variables so that the size of the largest BDD encountered is minimized. We show that an abstraction of this problem is NP-complete, and provide heuristic solutions for it. In some cases, the size of the BDD representing the transition relation of the product graph is too large. The partitioned transition relations problem deals with partially combining the BDDs and quantifying as many variables as possible, so that the time for computing the set of reachable states of the product graph is minimized. We offer heuristic solutions to this problem based on our algorithms for early quantification. The algorithms have been implemented and good experimental results have been achieved.

Automatic Datapath Abstraction In Hardware Systems

The biggest stumbling block to make formal verification widely acceptable is the state space explosion problem. Abstraction is used to simplify a design so that the number of reachable states is reduced. In this paper, we first introduce a concurrency model, called integer combinational/sequential (ICS), capable of describing hardware systems at high and low levels of abstractions. ICS uses finite relations, interpreted and uninterpreted integer functions and predicates, interpreted memory functions, and supports non-determinism and fairness constraints. As a subset, it includes finite-state systems with general fairness constraints. Verification in this framework is performed using language containment as follows. 1. For a subclass of “control-intensive” ICS models, we prove that finite small instantiations can be used to decide the properties without sacrificing accuracy. A linear time algorithm for recognizing these subsets is given. These results also hold for the standard finite-state systems and thus also provide some generic methods for automatic data abstraction for such systems. Using these results, we are able to verify a memory model by reducing integer data values to binary, and unbounded memory addresses to a small number. 2. For verifying properties of circuits with complex datapaths, the model can be executed symbolically to find the reachable states. In some cases, the set of reachable states is finite, and the verification can be completed exactly. In other cases, given n, the verifier checks that no errors of length less than n exist.

HSIS: A BDD-Based Environment for Formal Verification

Functional and timing verification are currently the bottlenecks in many design efforts. Simulation and emulation are extensively used for verification. Formal verification is now gaining acceptance in advanced design groups. This has been facilitated by the use of binary decision diagrams (BDDs). This paper describes the essential features of HSIS, a BDD-based environment for formal verification: 1. Open language design, made possible by using a compact and expressive intermediate format known as BLIF-MV. Currently, a synthesis subset of Verilog is supported. 2. Support for both model checking and language containment in a single unified environment, using expressivefairness constraints. 3. Efficient BDD-based algorithms. 4. Debugging environment for both language containment and model checking. 5. Automatic algorithms for the early quantification problem. 6. Support for state minimization using bisimulation and similar techniques. HSIS allows us to experiment with formal verification techniques on a variety of design problems. It also provides an environment for further research in formal verification.

BDD-Based Debugging Of Design Using Language Containment and Fair CTL

Formal design verification should be used to reveal bugs early in the design cycle. A tool exhibiting counter-examples (a debugger) is therefore essential. We describe debugging techniques for two important approaches to formal design verification: model checking using Computation Tree Logic ([Cla86]) and language containment using L-automata ([Kur90]).

Efficient ω-regular language containment

One method for proving properties about a design is by using L-automata [Kur90]. The main computation involves building the product machine of the system and specification, and then checking for cycles not contained in any of the cycle sets (these are sets of states specified by the user). In [Tou91] two methods were introduced for performing the above task; one involves computing the transitive closure of the product machine, and the other is an application of a method due to Emerson-Lei ([Eme86]). We have implemented both methods and extended them. We introduce a few generalpurpose operators on graphs and use them to construct efficient algorithms for the above task. Fast special checks are applied to find bad cycles early on. Initial experimental results are encouraging and are presented here.

Structural Symmetry and Model Checking

A fully automatic framework is presented for identifying symmetries in structural descriptions of digital circuits and CTL formulas and using them in a model checker. The set of sub-formulas of a formula is partitioned into equivalence classes so that truth values for only one sub-formula in any class need be evaluated for model checking. Structural symmetries in net-list descriptions of digital circuits and CTL formulas are formally defined and their relationship with the corresponding Kripke structures is described. A technique for automatic identification of structural symmetries is described that requires computation of the automorphism group of a suitable labeled directed graph. A novel fast algorithm for this problem is presented. Finally, experimental results are reported for BLIF-MV net-lists derived from Verilog.

Verification Using Uninterpreted Functions and Finite Instantiations

One approach to address the state explosion problem in verification of microprocessors with wide datapaths is to model variables as integers and datapath functions as uninterpreted ones. Verification then proceeds by either symbolically simulating this abstract model, or creating a small finite instantiation which contains all possible behaviors. In this paper, we first prove that the reachability problem for models with uninterpreted functions and predicates only of the form x=y, where both x and y are integer variables, is undecidable. However, such predicates are generally only needed in the property being checked and not in the model. For properties involving predicates of the forms x=term and x=y, we provide complete and partial verification techniques using finite instantiations respectively. Applications of these result to the verification of the control circuitry of superscalar microprocessors are provided, where one can verify various correctness properties using models with one or a few bit integers.

Language containment of non-deterministic omega-automata

Algorithms and techniques to determinize and complement Ω-automata with various forms of fairness constraints are investigated and implemented. A tool-box is constructed by supplementing these algorithms with less complex ones for certain special cases. Recently published constructions which are asymptotically optimum constitute some of the core routines. The principal use of these tools is in checking language containment between two non-deterministic automata. In language containment based verification, the need for this check may arise in two occasions: when checking whether a system satisfies a property expressed as a non-deterministic automaton, or, in hierarchical verification, where the more detailed system description must satisfy the more abstract specification.

A Unified Approach to Language Containment and Fair CTL Model Checking

Two important practical approaches to formal verification of finite-state systems are language containment using L-automata (LC) and Computation Tree Logic model checking (MC). Using either method, abstraction is used to model hardware systems. In most cases, it becomes necessary to remove some of the traces of the system introduced by abstraction. As constraints on the abstract models, one uses excepting conditions in LC, and fairness constraints in MC. In this paper, we argue that MC and LC are to some extent complementary. We then show how to perform both LC and MC in a unified environment, where the constraints can be a combination of excepting conditions and fairness constraints. We present an MC algorithm for Fair CTL, an extension of CTL capable of handling fairness constraints, which uses algorithms for LC as a subroutine. Advances made in LC checking can then be used to obtain an efficient algorithm. The algorithms have been implemented, and we comment on some experimental results.