Ramin Zanbaghi

An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT

A novel low power compact loop filter using a single amplifier biquad (SAB) network is presented for continuous-time (CT) delta-sigma (ΔΣ) modulators. This new technique reduces power consumption and die area by minimizing the number of active elements and simplifying the modulator topology. The new SAB network has a transfer function (TF) zero, which implements a local feedforward (FF) path in system-level diagram. By having a local FF branch embedded in the SAB network, the FF branches to the summing block in the SAB based feedforward modulator topology is reduced to half the number of FF branches in the conventional topology. Consequently, the SAB based modulator utilizes a switch-capacitor (SC) adder replacing the commonly used CT adder and the sample & hold blocks in the conventional architecture. The SAB based loop filter with reduced FF branches simplifies the design and implementation of the high-order continuous-time ΔΣ modulator. The proposed loop filter is a general filter, which can be used for both high and low oversampling ratios (OSRs). A 4th-order low pass continuous-time ΔΣ modulator is designed and implemented in 130 nm process to confirm the effectiveness of the proposed techniques. Within a 7.2 MHz signal bandwidth, the measured dynamic range and SFDR of this prototype IC are 80 dB and 83.1 dB, respectively, and the total power consumption of 13.7 mW.

\Delta \Sigma

This paper presents a new stage-sharing technique in a discrete-time (DT) 2-2 MASH delta-sigma (ΔΣ) ADC to reduce the modulator power consumption and chip die area. The proposed technique shares all active blocks between the two stages of the modulator. The 2-2 MASH modulator utilizes the second-order Chain of Integrators with Weighted Feed-forward Summation (CIFF) and the Cascade of Integrators with Distributed Feedback Branches (CIFB) architectures for the first and second stages, respectively. Using the proposed technique, the second integrator and the adder op-amps of the modulator first stage are shared with the first and second integrator op-amps of the second stage. In addition to the stage-sharing scheme, other changes are introduced to improve the modulator dynamic range (DR) and power dissipation. Measurement results show that the modulator designed in a 0.13 μm CMOS technology achieves 75 dB SNDR over a 5 MHz signal bandwidth with a clock frequency of 130 MHz, while dissipating less than 9 mW analog power.

Modulator Dissipating 13.7-mW

A novel low power hybrid (Active-Passive) loop filter using the single amplifier biquad (SAB) filter is presented. This new hybrid loop filter saves power consumption by reducing the number of active elements in the continuous-time sigma-delta modulator. Also, the core biquad filter allows the loop filter of a high-order modulator to be implemented by cascading low-order biquad sections, considerably easing the design and implementation of the high-order continuous-time sigma-delta modulator. The proposed loop filter is a general type of hybrid filter which could be used for the both high and low oversampling ratios (OSRs). Experiment on a 5th-order low pass continuous-time sigma-delta modulator with a bandwidth of 30MHz is conducted successfully and the results are presented.

A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2–2 MASH

This paper presents a new zero-optimization scheme for noise-coupled ΔΣ analog-to-digital converters (ADCs). The proposed technique enhances the signal-to-quantization-noise-ratio (SQNR) by optimizing noise-transfer-function (NTF) zero locations to get maximum in-band noise shaping. The amount of SQNR improvement using the new scheme depends on the order of the modulator. Therefore, zero optimization will be used in a first-order and a second-order modified noise-coupled ΔΣ ADCs. The proposed technique enhances the SQNR of the first-order and second-order noise-coupled ΔΣ modulators by 4.5dB and 8.5 dB, respectively.

\Delta \Sigma

This paper presents a new operational amplifier sharing technique for a continuous-time ΔΣ analog-to-digital converter (ADC). This technique saves power consumption by reducing the number of active elements in the modulator. Furthermore, the shared amplifier acts both as an adder and integrator in two different clock phases. The proposed technique also can be realized in a noise-coupled delta-sigma ADC. To verify the idea, a 2nd-order continuous-time ΔΣ modulator has been designed and simulated successfully with and without noise-coupling techniques.

Modulator Dissipating 16 mW Power

In this paper a new VCO-based MASH delta-sigma ADC structure is presented. The proposed architecture does not require any OTA-based analog integrators or integrating capacitors. Second-order noise shaping is achieved by using a VCO as an integrator in the feedback loop of the first stage and an open loop VCO quantizer in the second stage. Simple digital circuitry extracts the phase quantization error of the first stage as a pulse signal that is applied to the second stage. Based on the architecture, the input of the first VCO is a very small signal and the input of the second VCO is a two-level PWM signal. Therefore, the VCO non-linearity does not limit the overall ADC performance, mitigating the need for power hungry linearization methods. Behavioral-model simulations show a 70 dB SNDR improvement from a standalone open loop VCO-based ADC in the presence of nonlinearity.