Ramjay Pal

Modeling of dark characteristics of mercury cadmium telluride n+–p junctions

Dark dynamic impedance versus applied bias voltage characteristics of HgCdTe n þ –p junctions has been modelled here using a recently proposed [Infrared Phys. Technol. 43 (6) (2002) 317–326] analytical approach. The results of the analysis on two pixels from the same array are discussed to illustrate the advantage of this approach in identifying the possible source of variation of diode impedance among the diodes in an array. It has been shown that the contribution of dark current contributing mechanisms can be separated from each other in each diode. An idea of the dominant mechanism of the two sources of the ohmic current, namely surface leakage currents and contribution of dislocations intersecting the junction can also be had from temperature dependent study of shunt impedance. 2002 Elsevier Science B.V. All rights reserved.

Improved electrical properties of PbZrTiO3/BiFeO3 multilayers with ZnO buffer layer

In this study, the effect of ZnO buffer layer on the electrical properties of PbZrTiO3/BiFeO3 (PZT/BFO) multilayers has been reported. For this, PZT/BFO multilayers were spin-coated with and without ZnO buffer layer on platinized silicon wafers. X-ray diffraction results of both the films showed polycrystalline phase pure perovskite structure. Both the films show a dense and homogeneous grain structure. The electric properties of the films were measured. The ZnO buffered multilayer thin film showed ∼3 times improvement in remnant polarization compared to the multilayer thin film with no buffer. The buffered samples were found to have higher dielectric constant (1000 at 100u2009Hz) compared to that of sample (580 at 100u2009Hz)) with no buffer. Dielectric constants of both the films were found to be ∼30% tunable at 5u2009V. The buffered film also showed low leakage current density and higher dielectric breakdown compared to the multilayer thin film without buffer.

Growth and electrical properties of spin coated ultrathin ZrO2 films on silicon

Ultrathin (<50u2009nm) zirconium oxide (ZrO2) films are being intensively studied as high-k dielectrics for future metal-oxide-semiconductor (MOS) technology. In this paper, ultrathin ZrO2 films are deposited on silicon substrates by spin on deposition technique and annealed at 700u2009°C for different duration. The phase formation and morphological study have been performed by x-ray diffraction and scanning electron microscopy, respectively. Electrical properties of the films are investigated. The threshold voltages of the MOS structure were found to vary from −1.5u2009V to −2.5u2009V as the annealing time increases. The dielectric constants of the films are found to be 7.2–7.67 at 1 KHz. Leakage current of the films is found to increase with the annealing time. The dielectric breakdown field of the film is found to be 6.29–8.15 MV/cm.

Estimation of residual stress in Pb(Zr0.52Ti0.48)O3/BiFeO3 multilayers deposited on silicon

Thin multilayer films possess residual stress components which vary from microscopic to macroscopic scale. In this study, Pb(Zr0.52Ti0.48)O3/BiFeO3 (PZT-BFO) multilayer thin film is deposited via chemical solution deposition technique on silicon substrate. The microscopic and macroscopic residual stress components of the multilayer films are investigated. The average microscopic residual stress is estimated to be 791.15 MPa (tensile) by using x-ray diffraction technique; on the other hand, the average macroscopic stress is found to be 774.23 MPa (tensile) by using wafer curvature measurement technique. As the thermally grown SiO2 layer possesses compressive stress, the combined residual stress of the PZT-BFO multilayer and SiO2 will almost cancel each other. This is reasonably encouraging for integration of the multilayer in MEMS structures.

Electrical properties of ultrathin titanium dioxide films on silicon

Ultrathin (<50u2009nm) titanium dioxide (TiO2) films are being widely investigated as high-k dielectrics for future metal oxide semiconductor (MOS) technology. In this paper, ultrathin TiO2 films (∼20u2009nm) were deposited on silicon substrates by sputtering technique and subsequently annealed at 800u2009°C in oxygen environment for different durations (15–60u2009min). The annealed films were polycrystalline in nature with rutile phase. The value of dielectric constant was found to be 32–60 at 1u2009kHz measurement frequency. Threshold voltages of the MOS structures were found to vary from −0.1 to −0.5u2009V with the duration of annealing. Leakage current density (1u2009×u200910−2–1u2009×u200910−8u2009A/cm2 at 1u2009V) and dielectric breakdown fields (8.15–9.8 MV/cm) were observed to improve with annealing time.

Diffusion induced residual stress in comb-type microaccelerometer structure

This paper presents the effect of residual stresses due to deep boron diffusion on microaccelerometer structure. The microaccelerometer structure was simulated at various residual stresses using finite element method. The residual stress due to the diffusion process was estimated to be 450xa0MPa by using Raman spectroscopy. After fabricating the microaccelerometer structure, the deflection (~2xa0μm) of the moving comb fingers due to the stress was found to be in good agreement with the simulated value (2.1xa0μm). Sensitivity of the accelerometers was measured to be ~50xa0mV/g for 0–30xa0g range. In the initial range (0–5xa0g), the output of the accelerometers are depicting nonlinearity as anticipated from the simulated results.

Estimation of bending of micromachined gold cantilever due to residual stress

Electroplated gold is widely used as the material for the micromachined beam structures due to its excellent electrical and mechanical properties. This work attempts to analyze the surface micromachined gold cantilever beams under inherently present stress gradient. The structure is analyzed by using finite element method simulation at different intrinsic stress gradients. The gold layers are deposited using cyanide electroplating bath operated at different current densities. Residual stresses in electroplated gold layers deposited on photoresist coated silicon samples are estimated by using X-ray diffraction technique. Cantilever beam structures are fabricated using surface micromachining technique. The tip deflections of the fabricated cantilever beams are found to be ~16 and 8xa0μm corresponding to the 1.0 and 0.7xa0mA/cm2 current densities (mean), respectively. The corresponding intrinsic stress gradients are estimated to be −13.9 and −7.2xa0MPa/μm, respectively. Simulated and measured values of residual stresses are well matched.

Characterization deep boron diffused p ++ silicon layer

In recent years the boron impurity-based dissolved wafer process has been repeatedly demonstrated as a powerful tool for forming single crystal Si microstructures. However, there is very little report on detailed characterization of the deep boron diffused silicon layer. This paper presents the optimization of deep boron diffused p++ silicon layer (>10xa0μm thick) of boron concentration above 5xa0×xa01019xa0atoms/cm3. Detailed characterization of the p++ silicon layers, by using high resolution x-ray diffraction, secondary ion mass spectrometry, secondary electron micrograph are done. The optical behaviour of the p++ layers in mid-IR range is also carried out. The stress generated due to the deep diffusion is estimated to be 822xa0MPa by Raman spectroscopy.

Lapping assisted dissolved wafer process of silicon for MEMS structures

Dissolved wafer process (DWP) is being extensively used to fabricate complex micro-electro-mechanical system (MEMS) structures. Etching non-uniformity, increased surface roughness and duration of DWP is often influence MEMS devices yields. This paper presents a modified DWP involving lapping and polishing followed by chemical etching of silicon to release MEMS based structure. The lapping experiments are performed using silicon-carbide (SiC) and alumina (Al2O3) abrasive. The polishing of the silicon samples is also done. The lapped and polished surfaces are compared with etched silicon surfaces in KOH and EDP solutions. The lapping-polishing process is found to be 2.5 (Al2O3)–3 (SiC) times faster than a standard etching processes based on KOH and EDP solutions. The average roughness (Ra) of the lapped–polished silicon surfaces are found to be 19.2 and 32.9xa0nm corresponding to SiC and Al2O3 abrasive respectively. The Ra value of EDP and KOH etched silicon surfaces are found to be 16.2 and 238.3xa0nm respectively. Based on the lapping—polishing results, SiC based lapping followed by polishing of silicon surface can be used as an alternate of etching of silicon during DWP. In this paper, a two-step DWP, involving lapping-polishing followed by EDP chemical etching of silicon, is used to fabricate suspended comb-type microaccelerometer structure.

Be ion irradiation induced p- to n-type conversion in HgCdTe

Be ion implantation/irradiation in HgCdTe has been explored from the point of view of fabricating n region on p-type structures. Be implantation was carried out in vacancy doped p-type bulk HgCdTe crystals at 200KeV ion energy and a fluence of 1×1014ions∕cm2. Implanted samples were annealed at 150°C under nitrogen ambient for different durations. Be appears to be settling as an isoelectronic impurity in HgCdTe after the implant annealing process. A n-type region with reasonably good electron mobility is formed as a consequence of the redistribution of irradiation induced defects.