Raghvendra Sahai Saxena

Virtual Ground Technique for Crosstalk Suppression in Networked Resistive Sensors

Two-dimensional resistive sensor arrays that utilize shared row and column connections to simplify the interconnect complexity suffer from the crosstalk problem among its elements introduced due to the interconnection overloading. In this letter, we present a method of overcoming the problem of crosstalk by putting all of the row nodes at virtually equal potential using virtual ground of high-gain operational amplifiers (opamps) in negative feedback. The circuit, though it requires a large number of opamps, solves the crosstalk problem to a large extent and provides faster scanning. We verified the circuit functionality with PSPICE simulations. We have also derived the expressions of crosstalk rejection and sensitivity to show that, by using high-gain, low-noise opamps, we may get excellent performance.

Dual-Material-Gate Technique for Enhanced Transconductance and Breakdown Voltage of Trench Power MOSFETs

In this brief, we propose a new dual-material-gate-trench power MOSFET that exhibits a significant improvement in its transconductance and breakdown voltage without any degradation in on-resistance. In the proposed structure, we have split the gate of a conventional trench MOSFET structure into two parts for work-function engineering. The two gates share the control of the inversion charge in the channel. By using 2-D numerical simulation, we have shown that by adjusting the lengths of the two gates to allow equal share of the inversion charge by them, we get the optimum device performance. By using N+ poly-Si as a lower gate material and P+ poly-Si as an upper gate material, approximately 44% improvement in peak transconductance and 20% improvement in breakdown voltage may be achieved in the new device compared to the conventional trench MOSFET.

Analysis of Crosstalk in Networked Arrays of Resistive Sensors

In this paper, we present the analysis of the crosstalk limitation in 2-D resistive sensor arrays that utilize shared row and column connections for simplified interconnections. The mathematical expression for crosstalk among all of the elements introduced due to the interconnection overloading has been analytically derived and verified by the circuit simulations. Based on this analysis, we examined and proved that the solution of crosstalk and snapshot capability cannot be achieved simultaneously in networked resistive sensor arrays.

A Stepped Oxide Hetero-Material Gate Trench Power MOSFET for Improved Performance

In this brief, we propose a new stepped oxide hetero-material trench power MOSFET with three sections in the trench gate (an N+ poly gate sandwiched between two P+ poly gates) and having different gate oxide thicknesses (increasing from source side to drain side). The different gate oxide thickness serves the purpose of simultaneously achieving the following: 1) a good gate control on the channel charge and 2) a lesser gate-to-drain capacitance. As a result, we obtain higher transconductance as well as reduced switching delays, making the proposed device suitable for both RF amplification and high-speed switching applications. In addition, the sandwiched gate with different work-function gate materials modifies the electric field profile in the channel, resulting in an improved breakdown voltage. By using 2-D simulations, we have shown that the proposed device structure exhibits about 32% enhancement in breakdown voltage, 25% reduction in switching delays, 20% enhancement in peak transconductance, and 10% reduction in figure of merit (product of ON-resistance and gate charge) as compared to the conventional trench-gate MOSFET.

A New Strained-Silicon Channel Trench-Gate Power MOSFET: Design and Analysis

In this brief, we propose a new trench power MOSFET with strained-Si channel that provides lower on-resistance than the conventional trench MOSFET. Using a 20% Ge mole fraction in the Si1- Gex body with a compositionally graded Si1 - xGex buffer in the drift region enables us to create strain in the channel along with graded strain in the accumulation region. As a result, the proposed structure exhibits 40% enhancement in current drivability,28% reduction in the on-resistance, and 72% improvement in peak transconductance at the cost of only 12% reduction in the breakdown voltage when compared to the conventional trench-gate MOSFET. Furthermore, the graded strained accumulation region supports the confinement of carriers near the trench sidewalls, improving the field distribution in the mesa structure useful for a better damage immunity during inductive switching.

Effect of Excessive Bias Heating on a Titanium Microbolometer Infrared Detector

In a metal film infrared microbolometer, the responsivity is improved by high bias current to compensate for its low-temperature coefficient of resistance (TCR). However, what are the upper limits of this current without damaging the microbolometer element is not well understood. To study the effects of large bias current, we performed the destructive I-V measurements on an element of a 16 times 16 Ti-microbolometer array developed at our laboratory and report here the experimental observations of its electrical and physical damages. In this study, we performed the I-V measurements repeatedly on a microbolometer element and increased the final bias current in steps of 50 muA in each repetition. The effect of the heating due to I2R power dissipation has been analyzed at each step by monitoring I-V characteristics, specific detectivity and physical health. We report a significant decrease in the detectivity when bias stress is increased beyond 450 muA, which corresponds to the element temperature of 370degC. Further, we found that the resistance started decreasing, when the power dissipated and the element had increased to about 2.5 mW, resulting in a peaked I-V characteristics. This corresponds to the bias stresses more than 650 muA. Using a new I-V model, we extracted the temperature to be about 750degC at these peaks. A further increase in bias stress has resulted in the complete physical damage of the element.

A New LDMOSFET with Tunneling Junction for Improved On-State Performance

We propose a new laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) with a tunneling junction at the drain side to reduce its on-state resistance and improve the peak transconductance significantly, as compared with the conventional LDMOSFET device. Using 2-D numerical simulations in an ATLAS device simulator, we have shown that the proposed tunneling junction at the drain side results in 25% reduction in RON and 20% improvement in peak transconductance in an ~ 40-V device without any significant degradation in other performance parameters.

Polysilicon Spacer Gate Technique to Reduce Gate Charge of a Trench Power MOSFET

We propose a new trench gate power MOSFET with poly-Si spacers formed in the trench to work as gate material. This approach reduces the total gate charge and gate-to-drain capacitive coupling without affecting any other device performance parameter. Using 2-D numerical simulation on a ~25-V trench gate MOSFET, we have shown that using a 50-nm-wide spacer gate in a 1×1 μm trench may give >; 40% reduction in the gate-to-drain charge compared with the conventional device. The proposed technique has been shown to be better than the other techniques proposed earlier for reducing gate charge as it does not affect the gate control of the accumulation region charge or any other performance parameter, e.g., breakdown voltage, and can be implemented along with any of the existing techniques.

A New Buried-Oxide-In-Drift-Region Trench MOSFET With Improved Breakdown Voltage

In this letter, we propose a new trench-gate power MOSFET with buried oxide in its drift region that shows an improvement in the breakdown performance as compared to the conventional trench device due to a reduction in the vertical electric field. In addition, the proposed device shows about linear relation between the BV and R ON as compared to the 2.5th power relation in the conventional device.

Crosstalk suppression in networked resistive sensor arrays using virtual ground technique

In 2D resistive sensor arrays, the interconnections are reduced considerably by sharing rows and columns among various sensor elements in such a way that one end of each sensor is connected to a row node and other end connected to a column node. This scheme results in total N + M interconnections for N × M array of sensors. Thus, it simplifies the interconnect complexity but suffers from the crosstalk problem among its elements. We experimentally demonstrate that this problem can be overcome by putting all the row nodes at virtually equal potential using virtual ground of high gain operational amplifiers in negative feedback. Although it requires large number of opamps, it solves the crosstalk problem to a large extent. Additionally, we get the response of all the sensors lying in a column simultaneously, resulting in a faster scanning capability. By performing lock-in-amplifier based measurements on a light dependent resistor at a randomly selected location in a 4 × 4 array of otherwise fixed valued resistors, we have shown that the technique can provide 86 dB crosstalk suppression even with a simple opamp. Finally, we demonstrate the circuit implementation of this technique for a 16 × 16 imaging array of light dependent resistors.