Ramses Pierco

A 16 Channel High-Voltage Driver with 14 Bit Resolution for Driving Piezoelectric Actuators

A high-voltage, 16 channel driver with a maximum voltage of 72 volt and 14 bit resolution in a high-voltage CMOS (HV-CMOS) process is presented. This design incorporates a 14 bit monotonic by design DAC together with a high-voltage complementary class AB output stage for each channel. All 16 channels are used for driving a piezoelectric actuator within the control loop of a micropositioning system. Since the output voltages are static most of the time, a class AB amplifier is used, implementing voltage feedback to achieve 14 bit accuracy. The output driver consists of a push-pull stage with a built-in output current limitation and high-impedance mode. Also a protection circuit is added which limits the internal current when the output voltage saturates against the high-voltage rail. The 14 bit resolution of each channel is generated with a segmented resistor string DAC which assures monotonic by design behavior by using leapfrogging of the buffers used between segments. A diagonal shuffle layout is used for the resistor strings leading to cancellation of first order process gradients. The dense integration of 16 channels with high peak currents results in crosstalk, countered in this design by using staggered switching and resampling of the output voltages.

113Gb/s (10 x 11.3Gb/s) ultra-low power EAM driver array.

This paper presents an ultra-low power SiGe BiCMOS IC for driving a 10 channel electro-absorption modulator (EAM) array at 113Gb/s for wavelength division multiplexing passive optical network (WDM-PON) applications. With an output swing of 2.5V(pp), the EAM driver array consumes only 2.2W or 220mW per channel, 50% below the state of the art. Both the output swing and bias are configurable between 1.5 and 3.0V(pp) and 0.75-2.15V respectively.

100 Gbit/s serial transmission using a silicon-organic hybrid (SOH) modulator and a duobinary driver IC

100 Gbit/s three-level (50 Gbit/s OOK) signals are generated using a silicon-organic hybrid modulator and a BiCMOS duobinary driver IC at a BER of 8.5×10⁻⁵(<10⁻²). We demonstrate dispersion-compensated transmission over 5 km.

Real-time 100 Gb/s NRZ-OOK transmission with a silicon photonics GeSi electro-absorption modulator

We demonstrate single-wavelength, serial and real-time 100 Gb/s NRZ-OOK transmission over 500 m SSMF with a GeSi EAM implemented on a silicon photonics platform. The device was driven with 2 Vpp without 50 Ω termination, allowing a low-complexity solution for 400 GbE short-reach optical interconnects.

Towards efficient 100 Gb/s serial rate optical interconnects: A duobinary way

Recent advances in integrated opto-electronic devices and front end circuits have made it possible to efficiently transmit very high data rates over optical links for HPC/datacenter applications. This paper reviews our current progress towards serial 100-Gb/s optical interconnects, with emphasis on electrical duobinary (EDB) modulation.

Adaptive Transmit-Side Equalization for Serial Electrical Interconnects at 100 Gb/s Using Duobinary

The ever-increasing demand for more efficient data communication calls for new, advanced techniques for high speed serial communication. Although newly developed systems are setting records, off-line determination of the optimal equalizer settings is often needed. Well-known adaptive algorithms are mainly applied for receive-side equalization. However, transmit-side equalization is desirable for its reduced linearity requirements. In this paper, an adaptive sign–sign least mean square equalizer algorithm is developed applicable for an analog transmit-side feed-forward equalizer (FFE) capable of transforming non-return-to-zero modulation to duobinary (DB) modulation at the output of the channel. In addition to the derivation of the update strategy, extra algorithms are developed to cope with the difficult transmit–receive synchronization. Using an analog six tap bit-spaced equalizer, the algorithm is capable of optimizing DB communication of 100Gb/s over 1.5-m Twin-Ax cable. Both simulations and experimental results are presented to prove the capabilities of the algorithm demonstrating automated determination of FFE parameters, such that error-free communication is obtained (BER

A digitally controlled threshold adjustment circuit in a 0.13µm SiGe BiCMOS technology for receiving multilevel signals up to 80Gbps

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Analysis and design of a high power, high gain SiGe BiCMOS output stage for Use in a millimeter-wave power amplifier

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84 Gbit/s SiGe BiCMOS duobinary serial data link including Serialiser/Deserialiser (SERDES) and 5-tap FFE

In this paper, a high bandwidth digitally controlled threshold adjustment circuit is proposed which can be used for demodulating high-speed multi-level signals. Simulations of the bandwidth are presented together with measurements of the control currents to indicate the threshold adjustment capability. A bandwidth above 80GHz in a 0.13μm SiGe BiCMOS technology and a threshold tunable between ±160mV in steps of 0.6mV is achieved, allowing very precise control of the threshold level. This allows the circuit to accurately position the threshold on the eye-crossing of a high speed multi-level signals. By applying this circuit to demodulate a duobinary signal over a 40GHz channel, a data rate of up to 80Gbps can be achieved.

First real-time 100-Gb/s NRZ-OOK transmission over 2 km with a silicon photonic electro-absorption modulator

In this paper a high gain, high power output stage designed in a 250nm SiGe BiCMOS technology is presented. The used topology together with a discussion on the stability of the output stage is explained in detail. In order to increase the gain of the output stage and thus increases the attainable power added efficiency (PAE), positive feedback is used. Furthermore a formula predicting the input impedance of a common base transistor at high frequencies is deducted which explains and predicts the magnitude of the feedback mechanism. The output stage achieves a peak gain of 14.4dB at 31GHz with a maximum output power of 22dBm.