Rao R. Tummala

SOP: what is it and why? A new microsystem-integration technology paradigm-Moore's law for system integration of miniaturized convergent systems of the next decade

In the past, microsystems packaging played two roles: 1) it provided I/O connections to and from integrated circuits (ICs) or wafer-level packaging (WLP), and 2) it interconnected both active and passive components on system level boards, referred to as systems packaging. Both were accomplished by interconnections or multilayer wiring at the package or board level. More recently, the IC devices have begun to integrate not only more and more transistors, but also active and passive components on an individual chip, leading the community to believe that someday there may be a single-chip complete system, referred to as system-on-chip (SOC). This can be called horizontal or two-dimensional (2-D) integration of IC blocks in a single-chip toward end-product systems. The community began to realize, however, that such an approach presents fundamental, engineering, and investment limits, as well as computing and communication limits for wireless and wired systems over the long run. This led to 3-D packaging approaches, often referred to as system-in-package (SIP). The SIP, while providing major opportunities in both miniaturization and integration for advanced and portable electronic products, is a subsystem, limited by the CMOS process just like the SOC. Some existing and emerging applications, however, include sensors, memory modules and embedded processors with DRAMs. More recent 3-D solutions, which incorporate stacked package approaches, offer solutions toward faster time-to-market and business impediments that have plagued MCM deployment for the past decade. There is a new emerging concept called system-on-package (SOP). With SOP, the package, not the board, is the system. As such, SOP is beginning to address the shortcomings of both SOC and SIP, as well as traditional packaging which is bulky, costly, and lower in performance and reliability than ICs, in two ways: 1) It uses CMOS-based silicon for what it is good for, namely, for transistor integration, and the package, for what it is good for, namely, RF, optical, and digital integration by means of IC-package-system codesign. The SOP package, therefore, overcomes both the computing limitations and integration limitations of SOC, SIP, MCM, and traditional system packaging. It does this by having global wiring as well as RF, digital, and optical component integration in the package, not in the chip. The SOP, therefore, includes both active and passive components in thin-film form, in contrast with indiscrete or thick-film form, including embedded digital, RF, and optical components, and functions in a microminiaturized package or board.

The SOP for miniaturized, mixed-signal computing, communication, and consumer systems of the next decade

From cell phones to biomedical systems, modern life is inexorably dependent on the complex convergence of technologies into stand-alone products designed to provide a complete solution in small, highly integrated systems with computing, communication, biomedical and consumer functions. The concept of system-on-package (SOP) originated in the mid-1990s at the NSF-funded Packaging Research Center at the Georgia Institute of Technology. This can be thought of as a conceptual paradigm in which the package, and not the bulky board, as the system and the package provides all the system functions in one single module, not as an assemblage of discrete components to be connected together, but as a continuous merging of various integrated thin film technologies in a small package. In the SOP concept, this is accomplished by codesign and fabrication of digital, optical, RF and sensor functions in both IC and the package, thus distinguishing between what function is accomplished best at IC level and at package level. In this paradigm, ICs are viewed as being best for transistor density while the package is viewed as being best for RF, optical and certain digital-function integration. The SOP concept is demonstrated for a conceptual broad-band system called an intelligent network communicator (INC). Its testbed acts as both a leading-edge research and teaching platform in which students, faculty, research scientists, and member companies evaluate the validity of SOP technology from design to fabrication to integration, test, cost and reliability. The testbed explores optical bit stream switching up to 100 GHz, digital signals up to 5-20 GHz, decoupling capacitor integration concepts to reduce simultaneous switching noise of power beyond 100 W/chip, design, modeling and fabrication of embedded components for RF, microwave, and millimeter wave applications up to 60 GHz. This article reviews a number of SOP technologies which have been developed and integrated into SOP test bed. These are: 1) convergent SOP-based INC system design and architecture, 2) digital SOP and its fabrication for signal and power integrity, 3) optical SOP fabrication with embedded actives and passives, 4) RF SOP for high Q-embedded inductors, filters and other RF components, 5) mixed signal electrical test, 6) mixed signal reliability, and 7) demonstration of SOP by INC prototype system.

System on chip or system on package

The authors propose a new system design paradigm, the system on package, which uses electronic product reengineering to meet time-to-market and performance requirements. The system on package promises a higher return on investment than the system on chip.

Gigabit wireless: system-on-a-package technology

The system-on-a-package (SOP) concept is considered as the solution of future communication modules, where more functionality, better performance, low cost, and more integrity is needed. We demonstrate how SOP technology can address the integration platform for future communication systems, especially gigabit wireless communications. After the introduction of the SOP concept, we introduce the critical design building blocks which are required in a viable SOP technology: integrated passives, embedded RF functions, including high-performance filters and baluns, and integrated antenna technologies. Second, we review how the three-dimensional deployment of core elements, such as baluns, lumped inductors, capacitors, and resistors, as well as IF or low-pass filters, enables RF-SOP module development. We demonstrate how advanced radio architectures, including direct conversion, antenna diversity, and collaborative signal processing, are enabled using the SOP technology format. Various ceramic and organic material based multilayer packaging technologies have been used for building such integrated modules as well as circuit blocks. The critical issues and challenges for developing advanced communication platforms using the SOP approach are discussed.

Moore's law meets its match (system-on-package)

This paper describes the system-on-package (SOP) approach to miniaturization developed at the Microsystems Packaging Research Center at the Georgia Institute of Technology. Representing a radically different approach to systems, SOP combines IC with micrometer-scale thin film versions of discrete components, and it embeds everything in a new type of package so small that eventually handhelds will become anything from multi- to megafunction devices. It shrinks bulky circuit boards with their many components and makes them nearly disappear. Thus, SOP technology yields far more in system miniaturization than can be expected from Moores law, which deals only with transistors in ICs

Multichip packaging-a tutorial

Several aspects of the multichip module technology, including its functions, leverages, applications, and markets, are reviewed. All the packaging technologies used in multichip, such as sealing and encapsulation, heat removal, chip level connections, thin film, ceramic, and printed wiring, are discussed. The module corrections and electrical testing used in forming a high-performance or portable system are also discussed. >

Chip-last Embedded Active for System-On-Package (SOP)

Embedded active technology, in which thinned active chips are directly buried into a core or high-density-interconnect layers, is gaining more interest for ultra-miniaturization, increased functionality and better performance of SOP (system-on-package). In this study, chip-last embedded active concept is proposed to address some of process and reliability issues that current chip-first and chip-middle embedded active approaches have. The detailed process development for the first prototype of chip-last embedded active is described in this paper.

Electronic packaging in the 1990s-a perspective from America

The advanced packaging technologies that can be expected in the 1990s in high-performance systems are discussed in terms of chip connection, power distribution, heat removal, and thick- and thin-film wiring and package interconnections. The following topics are discussed in detail: (1) chip-level connection providing the required connections between the chip and the package; (2) power distribution to the chip and heat removal from the chip; (3) first-level packages providing all the necessary wiring, interconnections, and power distribution; (4) first-to-second level interconnections; and (5) second-level packages providing all the necessary wiring, connections, power distribution, and power supply connection. >

High density packaging in 2010 and beyond

As microsystems continue to move towards higher speed and microminiaturization, the demands for interconnection density both on the IC and the package increases tremendously. With the shift towards nano ICs by 2003 with 100 nm features, pitch of area array I/Os of the nano ICs will move towards 20-100 micron. Increasing system functionality and system-on-a-chip will place demands on the package to support extremely high digital clock speeds beyond 5 GHz, RF signals to 40 GHz, and optical data rates beyond 100 Gbps all on a single, highly integrated package or board. A completely new paradigm shift in high density packaging is required to meet these complex requirements. Current trends both in IC and systems packaging including SIP, wafer level packaging are steps in the right direction, but represent partial system solutions. The Packaging Research Center at Georgia Tech has been developing system-on-a-package (SOP) technology to integrate digital, RF, and optical, all on a multi-function, microminiaturized board. This paper reviews systems, IC, and high density packaging trends and summarizes the latest PRC developments in high density SOP packaging technology.

Cosintering process for glass-ceramic/copper multilayer ceramic substrate

In order to improve the electrical performance of the substrate for 3081 mainframe computers, a new material system consisting of glass-ceramic and copper metallurgy was developed for the system 390/ES9000 computers. The glass-ceramic package for the system 390/ES9000 is made up of 63 layers of green sheets screened with copper thick film paste and laminated under pressure to form a green body. The authors describe the challenges and solutions in cosintering the glass-ceramic and copper to form a dense package with the desired mechanical and electrical properties. A steam sintering process that is based on sound theoretical principles has been developed. This process has allowed packaging of a low dielectric constant ceramic with a high conductivity copper conductor. >