Rathindra N. Ghoshtagore

Recent Developments in Electrical Linewidth and Overlay Metrology for Integrated Circuit Fabrication Processes

Electrical linewidth measurements have been extracted from test structures replicated in planar films of monocrystalline silicon that were electrically insulated from the bulk-silicon substrate by a layer of silicon dioxide formed by separation by the implantation of oxygen (SIMOX) processing. Appropriate selection of the surface orientation of the starting material, the design and orientation of the structures features, and patterning by a lattice-plane selective etch provide features with planar, atomically smooth sidewalls and rectangular cross sections. The primary motivation for this approach is to attempt to overcome the serious challenge posed by methods divergence to the certification of linewidth reference-materials for critical-dimension (CD) instrument calibration and related tasks. To enhance the physical robustness of reference features with deep submicrometer linewidths, the new test structure embodies short reference-segment lengths and arbitrarily wide voltage taps. Facilities for reconciliation of measurements extracted from the same feature by all normally practiced techniques are also implemented. In overlay metrology, electrical inspection of two types of hybrid overlay targets allows pixel calibration of, and shift extraction from, the overlay instruments. The overall strategic focus of this research is to resolve methods-divergence issues and possibly to develop universal deep-submicrometer linewidth reference materials for CD instruments and techniques for instrument- and process-specific shift extraction for optical overlay metrology.

High-resolution transmission electron microscopy calibration of critical dimension (CD) reference materials

The National Institute of Standards and Technology and Sandia National Laboratories have developed a procedure for producing and calibrating critical dimension (CD), or linewidth, reference materials. These reference materials will be used to calibrate metrology instruments used in semiconductor manufacturing. The reference features, with widths down to 100 nm, are produced in monocrystalline silicon with all feature edges aligned to specific crystal planes. A two-part calibration of these linewidths is used: the primary calibration, with accuracy to within a few lattice plane thicknesses, is accomplished by counting the lattice planes across the sample as-imaged through use of high-resolution transmission electron microscopy. The secondary calibration is the high-precision electrical CD technique. In this paper, we describe the calibration procedure for these reference materials and estimate the related uncertainties.

Comparison of properties of electrical test structures patterned in BESOI and SIMOX films for CD reference-material applications

The National Institute of Standards and Technology (NIST) is exploring the feasibility of using artifacts fabricated on silicon-on-insulator (SOI) materials to quantify methods divergence, for critical dimension (CD) metrology applications. Test structures, patterned on two types of (110) SOI materials, SIMOX (Separation by IMplantation of OXygen) and BESOI (Bonded-and-Etched-back Silicon-on-Insulator), have been compared. In this paper, we describe results of electrical critical dimension (ECD) measurements and the relative performance of the test structures fabricated on the two SOI materials.

Extraction of sheet resistance from four-terminal sheet resistors replicated in monocrystalline films with nonplanar geometries

This paper describes limitations of conventional methods of extracting sheet resistance from four-terminal sheet resistors incorporated into electrical linewidth test structures that are patterned in [110] monocrystalline silicon-on-insulator (SOI) films. Nonplanar sections of these structures render the extraction of sheet resistance by conventional techniques subject to systematic errors. The errors are addressed here by algorithms incorporating the results of finite-element current flow analysis. The intended end application is to facilitate the use of the uniquely high repeatability and low cost of electrical critical dimension (CD) metrology as a secondary reference in a traceability path for CD-reference artifacts.

Measurement of patterned film linewidth for interconnect characterization

Test results from high-quality electrical and physical measurements on the same cross-bridge resistor test structure with approximately vertical sidewalls have shown differences in linewidth as great as 90 nm for selected conductive films. These differences were independent of design linewidth. As dimensions become smaller, the accurate measurement of the patterned conductor width is necessary to assure predictable timing performance of the interconnect system as well as control of critical device parameters.

Comparison of electrical CD measurements and cross-section lattice-plane counts of submicrometer features replicated in (100) silicon-on-insulator material

Electrical test structures of the type known as cross-bridge resistors have been patterned in (100) epitaxial silicon material that was grown on bonded and etched-back silicon-on- insulator (BESOI) substrates. The critical dimensions (CDs) of a selection of their reference segments have been measured electrically and by lattice-plane counting and they have been inspected by scanning-electron microscopy (SEM) cross-section imaging. The lattice-plane counting is performed on phase- contrast images made by high-resolution transmission-electron microscopy (HRTEM). The reference-segment features were aligned with <110> directions in the BESOI surface material. They were defined by a silicon micro-machining process which results in their sidewalls being nearly atomically planar and smooth and inclined at 54.737 degree(s) to the surface (100) plane of the substrate. This (100) implementation may usefully complement the attributes of the previously reported vertical-sidewall implementation for selected reference-material applications. The HRTEM, and electrical CD (ECD) linewidth measurements that are made on BESOI features of various drawn dimensions on the same substrate are being investigated to determine the feasibility of a CD traceability path that combines the low cost, robustness, and repeatability of the ECD technique and the absolute measurement of the HRTEM lattice-plane counting technique. Other novel aspects of the (100) Silicon-On- Insulator (SOI) implementation that are reported here are the ECD test-structure architecture and the making of HRTEM lattice-plane counts from both cross-sectional, as well as top-down, imaging of the reference features. This paper describes the design details and the fabrication of the cross- bridge resistor test structure. The long-term goal is to develop a technique for the determination of the absolute dimensions of the trapezoidal cross sections of the cross- bridge resistorss reference segments, as a prelude to making them available for dimensional reference applications.

Linewidth Measurement Intercomparison on a BESOI Sample

The effect of the instrument on the measurement must be known in order to generate an accurate linewidth measurement. Although instrument models exist for a variety of techniques, how does one assess the accuracy of these models? Intercomparisons between techniques which rely upon fundamentally different measurement physics can play an important role in model verification. We report here such an intercomparison. The average linewidth of a test pattern on a BESOI (Bonded and Etched-back Silicon on Insulator) sample, which is single crystal silicon with a buried insulating oxide, was measured using scanning electron microscopy (SEM) and electrical critical dimension (ECD) techniques. The higher conductivity of the BESOI sample compared to a previously measured SIMOX (another silicon on insulator technology) sample reduced the ECD uncertainty. Unexpected features in the SEM image were fit by modeling the cross sectional geometry of the line as a skewed trapezoid with deviations of a few tenths of a degree from the expected 90 degree angles. The SEM and ECD results differed by 0.67% of the electrical tap spacing, a nominal difference of 55 nm. This is larger than can be accounted for by known sources of measurement uncertainty.

Characterization of electrical linewidth test structures patterned in [100] silicon-on-insulator for use as CD standards

This paper describes the fabrication and measurement of the linewidths of the reference segments of cross-bridge resistors patterned in [100] Bonded and Etched Back Silicon-on-Insulator (BESOI) material. The critical dimensions (CD) of the reference segments of a selection of the cross-bridge resistor test structures were measured both electrically and by Scanning-Electron Microscopy (SEM) cross-section imaging.

Evaluation of surface depletion effects in single-crystal test structures for reference materials applications

Monocrystalline silicon test structures are being investigated for critical dimension (CD) reference materials applications. The goal of this work is to produce samples which do not exhibit the phenomenon of “methods divergence,” where the measurement of a single sample, fabricated in an electrical conductor, by multiple techniques leads to results that differ from one another by more than the total known error budgets of the measurements. In this paper, measurements are described to determine the sources of differences observed between electrical and other measurements.