Ravi Bonam

E-beam inspection of EUV mask defects: To etch or not to etch?

EUV Lithography is aimed to be inserted into mainstream production for sub-20nm pattern fabrication. Unlike conventional optical lithography, frequent defectivity monitors (adders, repeaters etc.) are required in EUV lithography. Due to sub-20nm pattern and defect dimensions e-beam inspection of critical pattern areas is essential for yield monitor. In previous work we showed sub-10nm defect detection sensitivity1 on patterned resist wafers. In this work we report 8-10× improvement in scan rates of etched patterns compared to resist patterns without loss in defect detection sensitivity. We observed good etch transfer of sub-10nm resist features. A combination of smart scan strategies with improved etched pattern scan rates can further improve throughput of e-beam inspection. An EUV programmed defect mask with Line/Space, Contact patterns was used to evaluate printability of defects and defect detection (Die-Die and Die-Database) capability of the e-beam inspection tool. Defect inspection tool parameters such as averaging, threshold value were varied to assess its detection capability and were compared to previously obtained results on resist patterns.

E-beam inspection of EUV programmed defect wafers for printability analysis

Understanding the effect of defect sizes and their impact on EUV lithography is an ongoing challenge due to continued scaling of devices [1], [2]. The objective of this study is to assess printability of defects on post develop photoresist wafers and their detection capability with an electron beam inspection tool on EUV resist for various patterns (Line/Space, Contacts). Total capture of defects is an important factor for assessing printability on photoresist patterned wafers and monitoring process window. In this work, we present a comparison of Die to Die (reference to programmed defect to sites on wafer) and Die to Database (program defect sites on wafer to design). A programmed defect test mask is used to understand the impact of printing mask defects at multiple lithography levels (ex. gate, metal etc.) at 20 and 14nm technology ground rules. It is designed with both additive and subtractive features at defect sizes ranging from 30nm to 1nm. The defect inspection tool parameters such as averaging, threshold value were varied to assess its detection capability.

Toward defect guard-banding of EUV exposures by full chip optical wafer inspection of EUV mask defect adders

The detection of EUV mask adder defects has been investigated with an optical wafer defect inspection system employing a methodology termed Die-to-“golden” Virtual Reference Die (D2VRD). Both opaque and clear type mask absorber programmed defects were inspected and characterized over a range of defect sizes, down to (4x mask) 40 nm. The D2VRD inspection system was capable of identifying the corresponding wafer print defects down to the limit of the defect printability threshold at approximately 30 nm (1x wafer). The efficacy of the D2VRD scheme on full chip wafer inspection to suppress random process defects and identify real mask defects is demonstrated. Using defect repeater analysis and patch image classification of both the reference die and the scanned die enables the unambiguous identification of mask adder defects.

Exploring EUV mask backside defectivity and control methods

The backside of photomasks have been largely ignored during the last several decades of development, with the exception of avoiding gross damage or defects, as almost all problems are far enough out of the focal plane to have minimal effect on imaging. Since EUV masks are reflective, and the column is held in a vacuum, scanners have been designed to utilize electrostatic chucking. With the chucking system for EUV, the requirements for the backside of the mask must be redefined to integrate concerns in substrate design, mask manufacturing, and usage. The two key concerns with respect to an electrostatic chuck are defects and durability. Backside defects can affect imaging, while potentially damaging or contaminating the tool, the mask, or even subsequently used masks. Compromised durability, from either usage or cleaning, can affect the ability of the chuck to hold the mask in place. In this study, these concerns are evaluated in three stages: minimizing defects created during mask fabrication, actions taken upon discovery of defects, and durability of the backside film with continued cleans and chucking. Data incorporated in this study includes: sheet resistance, film thickness, and optical inspection images. Incorporating the data from the three stages of fabrication, disposition, and lifetime will help us define how to structure backside EUV mask handling during mask manufacture and indicate what further solutions are needed as EUV technology transitions into manufacturing.

EUV mask and wafer defectivity: strategy and evaluation for full die defect inspection

Over the past few years numerous advancements in EUV Lithography have proven its feasibility of insertion into High Volume Manufacturing (HVM).1, 2 A lot of progress is made in the area of pellicle development but a commercially solution with related infrastructure is currently unavailable.3, 4 Due to current mask structure and unavailability of a pellicle, a comprehensive strategy to qualify (native defects) and monitor (adder defects) defectivity on mask and wafer is required for implementing EUV Lithography in High Volume Manufacturing. In this work, we assess multiple strategies for mask and wafer defect inspection including a two-fold solution to leverage resolution of e-beam inspection along with throughput of optical inspection are evaluated. Defect capture rates for inspections based on full-die, critical areas based on priority and hotspots based on design and prior inspection data are evaluated. Each strategy has merits and de-merits, particularly related to throughput, effective die coverage and computational overhead. A production ready EUV Exposure tool was utilized to perform exposures at the IBM EUV Center of Excellence in Albany, NY for EUV Lithography Development along with a fully automated line of EUV Mask Infrastructure tools. We will present strategies considered in this study and discuss respective results. The results from the study indicate very low transfer rate of defect detection events from optical mask inspection. They also suggest a hybrid strategy of utilizing both optical and e-beam inspection can provide a comprehensive defect detection which can be employed in High Volume Manufacturing.

EUV mask black border evolution

The black border is a frame created by removing all the multilayers on the EUV mask in the region around the chip. It is created to prevent exposure of adjacent fields when printing an EUV mask on a wafer. Papers have documented its effectiveness. As the technology transitions into manufacturing, the black border must be optimized from the initial mask making process through its life. In this work, the black border is evaluated in three stages: the black border during fabrication, the final sidewall profile, and extended lifetime studies. This work evaluates the black border through simulations and physical experiments. The simulations address concerns for defects and sidewall profiles. The physical experiments test the current black border process. Three masks are used: one mask to test how black border affects the image placement of features on mask and two masks to test how the multilayers change through extended cleans. Data incorporated in this study includes: registration, reflectivity, multilayer structure images and simulated wafer effects. By evaluating the black border from both a mask making perspective and a lifetime perspective, we are able to characterize how the structure evolves. The mask data and simulations together predict the performance of the black border and its ability to maintain critical dimensions on wafer. In this paper we explore what mask changes occur and how they will affect mask use.

Printability and actinic AIMS review of programmed mask blank defects

We report on the printability, mitigation and actinic mask level review of programmed substrate blank pit and bump defects in a EUV lithography test mask. We show the wafer printing behavior of these defects exposed with an NXE:3300 EUV lithography scanner and the corresponding mask level actinic review using the AIMSTM tool. We will show which categories of these blank substrate defects print on wafer and how they can be mitigated by hiding these defects under absorber lines. Furthermore we show that actinic AIMSTM mask review images of these defects, in combination with a simple thresholded resist transfer model, can accurately predict their wafer printing profiles. We also compare mask level actinic AIMSTM to top down mask SEM review in their ability to detect these defects.

Comprehensive analysis of line-edge and line-width roughness for EUV lithography

Pattern transfer fidelity is always a major challenge for any lithography process and needs continuous improvement. Lithographic processes in semiconductor industry are primarily driven by optical imaging on photosensitive polymeric material (resists). Quality of pattern transfer can be assessed by quantifying multiple parameters such as, feature size uniformity (CD), placement, roughness, sidewall angles etc. Roughness in features primarily corresponds to variation of line edge or line width and has gained considerable significance, particularly due to shrinking feature sizes and variations of features in the same order. This has caused downstream processes (Etch (RIE), Chemical Mechanical Polish (CMP) etc.) to reconsider respective tolerance levels. A very important aspect of this work is relevance of roughness metrology from pattern formation at resist to subsequent processes, particularly electrical validity. A major drawback of current LER/LWR metric (sigma) is its lack of relevance across multiple downstream processes which effects material selection at various unit processes. In this work we present a comprehensive assessment of Line Edge and Line Width Roughness at multiple lithographic transfer processes. To simulate effect of roughness a pattern was designed with periodic jogs on the edges of lines with varying amplitudes and frequencies. There are numerous methodologies proposed to analyze roughness and in this work we apply them to programmed roughness structures to assess each technique’s sensitivity. This work also aims to identify a relevant methodology to quantify roughness with relevance across downstream processes.

An OCD perspective of line edge and line width roughness metrology

Metrology of nanoscale patterns poses multiple challenges that range from measurement noise, metrology errors, probe size etc. Optical Metrology has gained a lot of significance in the semiconductor industry due to its fast turn around and reliable accuracy, particularly to monitor in-line process variations. Apart from monitoring critical dimension, thickness of films, there are multiple parameters that can be extracted from Optical Metrology models3. Sidewall angles, material compositions etc., can also be modeled to acceptable accuracy. Line edge and Line Width roughness are much sought of metrology following critical dimension and its uniformity, although there has not been much development in them with optical metrology. Scanning Electron Microscopy is still used as a standard metrology technique for assessment of Line Edge and Line Width roughness. In this work we present an assessment of Optical Metrology and its ability to model roughness from a set of structures with intentional jogs to simulate both Line edge and Line width roughness at multiple amplitudes and frequencies. We also present multiple models to represent roughness and extract relevant parameters from Optical metrology. Another critical aspect of optical metrology setup is correlation of measurement to a complementary technique to calibrate models. In this work, we also present comparison of roughness parameters extracted and measured with variation of image processing conditions on a commercially available CD-SEM tool.

Detection of Printable EUV Mask Absorber Defects and Defect Adders by Full Chip Optical Inspection of EUV Patterned Wafers

The ability to rapidly detect both printable EUV mask adder defects as well as mask absorber defects across the entire mask image field is a key enabler for EUV lithography. Current optical wafer-based inspection techniques are only capable of detecting repeater defects on a die-to-die basis for chiplets within the image field. Larger server-type chips that encompass the entire mask image field cannot rely on such a scheme, since the presence of the defect in every die prevents their detection. In this paper, a prototype optical wafer defect inspection methodology designed to detect repeater defects over the entire image field, termed die-to-baseline reference die (D2BRD), is investigated. The sensitivity of this inspection technique is demonstrated and compared to eBeam inspection over a range of defect sizes for both opaque and clear type mask absorber programmed defects. Moreover, the D2BRD methodology is used to monitor printing defect adders present in a lithographic defect test mask, as well as 7-nm BEOL layers. Using defect repeater analysis, SEM review and patch image classification of full chip wafer inspections over several mask cycles, the D2BRD scheme is shown to allow the unambiguous identification of mask adder defects, while suppressing random process defects. This methodology has the potential to define the risk assessment of mask adder defects in the absence of an EUV pellicle, and can play an integral part of the wafer print protection strategy.