Nelson Felix

Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress

Abstract. Process-induced overlay errors are a growing problem in meeting the ever-tightening overlay requirements for integrated circuit production. Although uniform process-induced stress is easily corrected, nonuniform stress across the wafer is much more problematic, often resulting in noncorrectable overlay errors. Measurements of the wafer geometry of free, unchucked wafers give a powerful method for characterization of such nonuniform stress-induced wafer distortions. Wafer geometry data can be related to in-plane distortion of the wafer pulled flat by an exposure tool vacuum chuck, which in turn relates to overlay error. This paper will explore the relationship between wafer geometry and overlay error by the use of silicon test wafers with deliberate stress variations, i.e., engineered stress monitor (ESM) wafers. A process will be described that allows the creation of ESM wafers with nonuniform stress and includes many thousands of overlay targets for a detailed characterization of each wafer. Because the spatial character of the stress variation is easily changed, ESM wafers constitute a versatile platform for exploring nonuniform stress. We have fabricated ESM wafers of several different types, e.g., wafers where the center area has much higher stress than the outside area. Wafer geometry is measured with an optical metrology tool. After fabrication of the ESM wafers including alignment marks and first level overlay targets etched into the wafer, we expose a second level resist pattern designed to overlay with the etched targets. After resist patterning, relative overlay error is measured using standard optical methods. An innovative metric from the wafer geometry measurements is able to predict the process-induced overlay error. We conclude that appropriate wafer geometry measurements of in-process wafers have strong potential to characterize and reduce process-induced overlay errors.

Simultaneous measurement of optical properties and geometry of resist using multiple scatterometry targets

Optical properties (n and k) of the material films under measurement are commonly assumed invariant and fixed in scatterometry modeling. This assumption keeps the modeling simple by limiting the number of floating parameters in the model. Such scatterometry measurement has the potential to measure with high precision some of the profile parameters (critical dimension, sidewall angle). The question is: if the optical properties modeled as fixed are actually changing, would this modeling assumption impact the accuracy of reported geometrical parameters? Using the example of a resist profile measurement, we quantify the bias effect of unmodeled variation of optical properties on the accuracy of the reported geometry by utilizing a traditional fixed n and k model. With a second model, we float an additional optical parameter and lower the bias of the reported values, at the expense of slightly increased noise of the measurement (more floating parameters, less precision). Finally, we extend our multistack approach (previously introduced as an enabler to the product-driven material characterization methodology) to augment the spectral information and increase both precision and accuracy through the simultaneous modeling of multiple targets.

Overlay improvement roadmap: strategies for scanner control and product disposition for 5-nm overlay

To keep pace with the overall dimensional shrink in the industry, overlay capability must also shrink proportionally. Unsurprisingly, overlay capability < 10 nm is already required for currently nodes in development, and the need for multi-patterned levels has accelerated the overlay roadmap requirements to the order of 5 nm. To achieve this, many improvements need to be implemented in all aspects of overlay measurement, control, and disposition. Given this difficult task, even improvements involving fractions of a nanometer need to be considered. These contributors can be divided into 5 categories: scanner, process, reticle, metrology, and APC. In terms of overlay metrology, the purpose is two-fold: To measure what the actual overlay error is on wafer, and to provide appropriate APC feedback to reduce overlay error for future incoming hardware. We show that with optimized field selection plan, as well as appropriate within-field sampling, both objectives can be met. For metrology field selection, an optimization algorithm has been employed to proportionately sample fields of different scan direction, as well as proportional spatial placement. In addition, intrafield sampling has been chosen to accurately represent overlay inside each field, rather than just at field corners. Regardless, the industry-wide use of multi-exposure patterning schemes has pushed scanner overlay capabilities to their limits. However, it is now clear that scanner contributions may no longer be the majority component in total overlay performance. The ability to control correctable overlay components is paramount to achieving desired performance. In addition, process (non-scanner) contributions to on-product overlay error need to be aggressively tackled, though we show that there also opportunities available in active scanner alignment schemes, where appropriate scanner alignment metrology and correction can reduce residuals on product. In tandem, all these elements need to be in place to achieve the necessary overlay roadmap capability for current development efforts.

EUV patterning successes and frontiers

The feature scaling and patterning control required for the 7nm node has introduced EUV as a candidate lithography technology for enablement. To be established as a front-up lithography solution for those requirements, all the associated aspects with yielding a technology are also in the process of being demonstrated, such as defectivity process window through patterning transfer and electrical yield. This paper will review the current status of those metrics for 7nm at IBM, but also focus on the challenges therein as the industry begins to look beyond 7nm. To address these challenges, some of the fundamental process aspects of holistic EUV patterning are explored and characterized. This includes detailing the contrast entitlement enabled by EUV, and subsequently characterizing state-of-the-art resist printing limits to realize that entitlement. Because of the small features being considered, the limits of film thinness need to be characterized, both for the resist and underlying SiARC or inorganic hardmask, and the subsequent defectivity, both of the native films and after pattern transfer. Also, as we prepare for the next node, multipatterning techniques will be validated in light of the above, in a way that employs the enabling aspects of EUV as well. This will thus demonstrate EUV not just as a technology that can print small features, but one where all aspects of the patterning are understood and enabling of a manufacturing-worthy technology.

Smaller, smarter, faster, and more accurate: the new overlay metrology

With the introduction of double patterning, overlay capability below 5nm is required for optical lithography density scaling to the 22nm node and beyond. Commensurate overlay metrology must enable dense sampling of all patterned area to control single-nanometer systematic sources of error among an increasing number of device layers. This translates to the need for sub-second measurement of microscopic targets representing multiple layers within a metrology tool field of view, all while improving accuracy. Blossom (BLO) is the overlay metrology of record for the IBM 32nm technology. As we will describe here, the densely packed array of layers represented in a single BLO target has enabled us to conduct within-field in-line sampling on our most critical layers. We will also report the significant improvements to metrology performance that have resulted from our migration of BLO technology to a new measurement platform. In addition, as 22nm development proceeds, we are shrinking our overlay targets further. A target suitable for within-chip insertion, a 10μm square micro-Blossom (μBLO) target, can accommodate up to 8 layers. Correlation of μBLO to BLO measurements on a layer pair shows excellent agreement, and despite an approximately 10X area shrink relative to BLO, the μBLO measurement uncertainty remains comfortably below 0.5nm. Our paper presents details of our target layout, measurement, and analysis approach. In addition, we detail data representative of overlay variation in state-of-the-art lithographic processes, along with our outlook for overlay metrology implementation for future technologies.

Predicting substrate-induced focus error

The ever-shrinking lithography process window dictates that we maximize our process window, minimize process variation, and quantify the disturbances to an imaging process caused upstream of the imaging step. Relevant factors include across-wafer and wafer-to-wafer film thickness variation, wafer flatness, wafer edge effects, and design-induced topography. We present our effort to predict design-induced focus error hot spots based on prior knowledge of the wafer surface topography. This knowledge of wafer areas challenging the edge of our process window enables a constructive discussion with our design and integration team to prevent or mitigate focus error hot spots upstream of the imaging process.

Design technology co-optimization assessment for directed self-assembly-based lithography: design for directed self-assembly or directed self-assembly for design?

Abstract. We report a systematic study of the feasibility of using directed self-assembly (DSA) in real product design for 7-nm fin field effect transistor (FinFET) technology. We illustrate a design technology co-optimization (DTCO) methodology and two test cases applying both line/space type and via/cut type DSA processes. We cover the parts of DSA process flow and critical design constructs as well as a full chip capable computational lithography framework for DSA. By co-optimizing all process flow and product design constructs in a holistic way using a computational DTCO flow, we point out the feasibility of manufacturing using DSA in an advanced FinFET technology node and highlight the issues in the whole DSA ecosystem before we insert DSA into manufacturing.

EUV processing and characterization for BEOL

The successful demonstration of 637 wafer exposures in 24 hours on the EUV scanner at the IBM EUV Center for Excellence in July marked the transition from research to process development using EUV lithography. Early process development on a new tool involves significant characterization, as it is necessary to benchmark tool performance and process capability. This work highlights some key learning from early EUV process development with a focus on identifying the largest sources of variability for trench and via hole patterning through the patterning process. The EUV scanner demonstrated stable overlay on a 40 lot test run using integrated wafers. The within field and local critical dimension uniformity (CDU) are the largest contributors to CD variations. The line edge roughness (LER) and line width roughness (LWR) in EUV resist will be compared to the post etch value to determine the effect of processing. While these numbers are generally used to describe the robustness of 1D trenches or circular vias, the need to accurately evaluate the printability of irregular 2D features has become increasingly important. In the past 5 years, models built from critical dimension scanning electron microscope (CDSEM) contours has become a hot topic in computational lithography. Applying this methodology, the CDSEM contour technique will be used to assess the uniformity of these irregular patterns in EUV resist and after etching. CDSEM contours also have additional benefits for via pattern characterization.

Comparison of left and right side line edge roughness in lithography

The left side and right side line edge roughnesses (LER) of a line are compared for different conditions, such as through pitch, through critical dimension (CD), from horizontal to vertical line direction, from litho to etch. The investigation shows that the left and right side LER from lithography process are the same, however, the metrology can cause a 4-25% increase in the measured right side LER. The LER difference is related to the CDSEM e-beam scan direction.

DSA patterning options for FinFET formation at 7nm node

Several 27nm-pitch directed self-assembly (DSA) processes targeting fin formation for FinFET device fabrication are studied in a 300mm pilot line environment, including chemoepitaxy for a conventional Fin arrays, graphoepitaxy for a customization approach and a hybrid approach for self-aligned Fin cut. The trade-off between each DSA flow is discussed in terms of placement error, Fin CD/profile uniformity, and restricted design. Challenges in pattern transfer are observed and process optimization are discussed. Finally, silicon Fins with 100nm depth and on-target CD using different DSA options with either lithographic or self-aligned customization approach are demonstrated.