Raymond Albert Fillion

Overlay high-density interconnect: a chips-first multichip module technology

A high-density interconnection (HDI) technology that involves placing bare chips into cavities on a base substrate and fabricating the thin-film interconnect structure on top of the components is described. The interconnects to the chip I/O pads are formed as part of the thin-film fabrication process, thus eliminating the need for wire bonds, tape-automated bonds (TABs), or solder bumps. The need for advanced packaging and interconnection and the standard chips-last multichip module (MCM) technologies are reviewed. The HDI chips-first MCM technologys IC pretest requirements and approaches, substrate and packaged parts test, and substrate packaging are discussed.<<ETX>>

The single chip versus multichip packaging option for digital CMOS in the 1990s

The level of functional density achievable in digital CMOS logic chips is so high that in the past systems implementations by multichip module (MCM) packaging appear to have been unnecessary, because the system was usually made up of only a few chips. However, rapidly increasing system sizes anticipated in the future will require many VLSI/ULSI CMOS chips per system, operating at near 100 MHz clock frequency. The authors have, therefore, reexamined the single-chip versus MCM packaging option for digital CMOS for the 1990s. They conclude that, for large-scale CMOS logic systems constructed by the use of many state-of-the-art VLSI/ULSI chips, the MCM packaging approach gives a manyfold improvement in packing density (3-8*), performance (up to 1.4*), and cost (1.2*) over the SCM packaging approach. >

The GE high density overlay MCM interconnect method solves high power needs of GaAs system design

As electronic systems signals and clock rates exceed 100 MHz, designers must consider the use of emerging high performance digital GaAs chip technology. Because GaAs parts do not yield at the high rates of more mature silicon technology devices, it is presently infeasible to build monolithic wafer scale integration (WSI) with GaAs technology. A hybrid wafer scale integration (HWSI) approach has been developed to overcome the limits of monolithic approaches, including the ability to provide for multichip module (MCM) process optimizations serving low IR loss requirements for power delivery, and use of overlay interconnect, first placing the chip into a structure for the most advantageous thermal management.<<ETX>>