Michael Gdula

A 36-chip multiprocessor multichip module made with the General Electric high density interconnect technology

A unique packaging and interconnect technology was used to build a multichip, four-CPU-element, pipeline parallel processing computer module using Texas Instruments TMS320C25 digital signal processors and companion circuits. The technology allowed a greater than fifteen-fold reduction in area over conventional chip packages mounted with printed circuit board methods. Reduced interconnect capacitance coupled with elimination of conventional package parasitics allowed clocking of commercial 40 MHz parts to nearly 90 MHz.<<ETX>>

A high-speed, high-density multiprocessing module made with the general electric high-density interconnect technology

Digital signal processing technology has developed to the point that conventional chip packaging and circuit board technologies are limiting system performance. Recent advances in Multichip Module (MCM) technology from several sources permit a higher performance and a more dense alternative for constructing DSP-based circuits. GE has developed one of the most space efficient and highest performance MCM fabrication processes. This process was used to build a multichip, four-CPU-element, pipeline parallel processing computer module. Off-the-shelf DSP chips (Texas Instruments TMS320C25), static RAM, dual-ported RAM, and logic chips were used. This multichip digital signal processor with module design and fabrication has been supported by Defense Advanced Research Projects Agency (DARPA). Circuit size was reduced 15-fold over conventional chip packages and printed circuit board methods. An additional benefit of this technology, reduced interconnect capacitance coupled with elimination of conventional package parasitics, allowed doubling of the commercial 40-MHz clock rate to more than 80 MHz.

The single chip versus multichip packaging option for digital CMOS in the 1990s

The level of functional density achievable in digital CMOS logic chips is so high that in the past systems implementations by multichip module (MCM) packaging appear to have been unnecessary, because the system was usually made up of only a few chips. However, rapidly increasing system sizes anticipated in the future will require many VLSI/ULSI CMOS chips per system, operating at near 100 MHz clock frequency. The authors have, therefore, reexamined the single-chip versus MCM packaging option for digital CMOS for the 1990s. They conclude that, for large-scale CMOS logic systems constructed by the use of many state-of-the-art VLSI/ULSI chips, the MCM packaging approach gives a manyfold improvement in packing density (3-8*), performance (up to 1.4*), and cost (1.2*) over the SCM packaging approach. >

The GE high density overlay MCM interconnect method solves high power needs of GaAs system design

As electronic systems signals and clock rates exceed 100 MHz, designers must consider the use of emerging high performance digital GaAs chip technology. Because GaAs parts do not yield at the high rates of more mature silicon technology devices, it is presently infeasible to build monolithic wafer scale integration (WSI) with GaAs technology. A hybrid wafer scale integration (HWSI) approach has been developed to overcome the limits of monolithic approaches, including the ability to provide for multichip module (MCM) process optimizations serving low IR loss requirements for power delivery, and use of overlay interconnect, first placing the chip into a structure for the most advantageous thermal management.<<ETX>>