Raymond Foley

Sensorless Current Estimation and Sharing in Multiphase Buck Converters

Virtually, all of the current-sensing methods for power converters presented to date rely on a priori knowledge of circuit parameters to ensure accurate current measurement. Also, the advent of digital control in low-cost high-volume applications-such as voltage regulator modules (VRMs) for computer microprocessors-has added the challenge and cost of analog-to-digital conversion to this task. This paper introduces a parameter-independent, sensorless current-sharing algorithm for multiphase power converters based on gradient estimation via low-frequency perturbation of the per-phase duty cycles, thus eliminating the need for current sensing. Measures of only the input and output voltages are required, so the analog-to-digital converter (ADC) and communication/interfacing overhead is low. The algorithm is demonstrated through both simulation and experimental implementation using a digitally controlled three-phase buck converter.

Multiphase digital pulsewidth modulator

This letter describes a digital pulsewidth modulator that enables the generation of a large, adjustable number of pulsewidth modulated (PWM) outputs of programmable duty cycle and dead time, yet requiring just a small, fixed architecture. The design achieves a resolution of 255 ps using a composite PWM strategy that also minimizes clock frequency and area. It provides a practical solution to the problem of efficiently generating multiple high-resolution gate-drive signals and is particularly suited to the next generation of synchronously switched multiphase voltage regulator modules

Parasitic inductance effect on switching losses for a high frequency Dc-Dc converter

This work examines the impact of packaging parasitics on the efficiency of a synchronous DC-DC buck converter. An analytical model of the losses in the converter is developed and this is compared to practical results at switching frequencies in the range of 1-2 MHz. The effect that the packaging parasitic inductance has on efficiency is highlighted by predicting the expected losses from a converter with optimised packaging parasitics.

An area-efficient digital pulsewidth modulation architecture suitable for FPGA implementation

This paper describes a digital pulsewidth modulator (DPWM) designed for FPGA implementation. A novel multi-output pulsewidth modulation scheme is introduced, as is a frequency calibration method suitable for use on FPGAs. The resulting architecture provides versatile output waveforms with high resolution, but with a small area requirement.

Technology Roadmapping for Power Supply in Package (PSiP) and Power Supply on Chip (PwrSoC)

This paper presents a review and summary of the PSMA “PSiP2PwrSoC” special project that investigated the technology and performance underpinning recent commercial developments in Power Supply in Package and Power Supply on Chip. The results of this study are based on the identification of more than 28 commercial products, six of which were analyzed in detail, both physically and electrically. The methodology of the project is described and some of the salient results of this benchmarking effort are presented. In this study, a representative subset of the available commercial products was selected and a comprehensive physical, electrical and thermal performance analysis was carried out. The objectives were to identify the components, materials and assembly technologies used, and to determine if the drive toward greater integration and higher power density affected the performance of newer devices. The results of the analysis were then used to determine the current state of the technology in this application space, to show how it has developed to date and to predict how it might progress in the future. These results are presented in a generic format that does not identify individual products. This project was co-sponsored by the PSMA and member companies. The final report of the project, which includes more detailed information on the reviews described here as well as considerable trending analysis, is now available.

Technology roadmapping for Power Supply in Package (PSiP) and Power Supply on Chip (PwrSoC)

This paper presents a review and summary of the PSMA ¿PSiP2PwrSoC¿ Special Project that investigated the technology and performance underpinning recent commercial developments in Power Supply in Package and Power Supply on Chip. The results of the study are based on the identification of more than 28 commercial products, 6 of which were analyzed in detail, both physically and electrically. The methodology of the project is described and some of the salient results of this benchmarking effort are presented. In this work, a representative subset of the available commercial products was selected and a comprehensive physical, electrical and thermal performance analysis was carried out. The main aims of this analysis were to identify the components, materials and assembly technologies used, and to determine if the drive towards greater integration and higher power density affected the performance of newer devices. The results of the analysis were then used to determine the current state of the technology in this application space, to show how it has developed to date and to predict how it might progress in the future. These results are presented in a generic format that does not identify individual products. This project was co-sponsored by the PSMA and member companies. The final report of the project, which includes more detailed information on the reviews described here as well as considerable trending analysis, is now available.

A Versatile Digital Pulsewidth Modulation Architecture with Area-Efficient FPGA Implementation

This paper describes a multi-output digital pulsewidth modulator (DPWM) that generates versatile waveforms suitable for use in a typical multi-phase interleaved switching DC-DC buck converter. A heterogenous DPWM is proposed that achieves a resolution of 255 ps, facilitating multi-megahertz switching frequencies. A novel global architecture is also introduced that exploits the phased nature of the interleaved buck converter, limiting the number of required multiplexers/comparators and enabling a large, adjustable number of variable-frequency pulsewidth modulated outputs to be generated using a small, xed architecture with programmable duty-cycles and dead-times

A 20 MHz 200-500 mA Monolithic Buck Converter for RF Applications

In an RF system power amplifiers (PAs) typically consume the most power. This paper presents a buck converter design optimised for a wideband code division multiple access (WCDMA) PA. The design approach taken focuses on the optimization of switch sizing based on the overall power losses of the system including the output inductor losses. The converter is optimised for 20 MHz switching and output currents in the range of 200-500 mA. Experimented results are presented on the fabricated converter, with a maximum measured efficiency of 82%.

Sensorless Current-Sharing in Multiphase Power Converters

This paper presents a novel, sensorless, current-sharing, algorithm for multiphase power converters, based on gradient estimation via low-frequency perturbation of the duty-cycle input to each phase. The algorithm eliminates the need for current sensing, and is particularly useful when allied to a digital controller, because the only analogue-to-digital conversions necessary are measurements of the output and input voltages

Design and optimisation of a high current, high frequency monolithic buck converter

The detailed design and optimisation of a high current monolithic point-of-load (POL) buck converter is presented in this paper. The approach taken is to identify the major design issues which account for power losses and represent them as a function of the power device width. Having identified these loss sources and quantified them, the optimum power device sizes are obtained for a converter with a 20 MHz switching frequency.