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Dive into the research topics where Raymond T. Lee is active.

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Featured researches published by Raymond T. Lee.


IEEE Electron Device Letters | 1994

Characterization and optimization of metal etch processes to minimize charging damage to submicron transistor gate oxide

Ming-Ren Lin; Peng Fang; Felicia Heiler; Raymond T. Lee; Rajat Rakkhit; Lewis Shen

Two metal etch systems are compared in terms of their impacts on submicron transistor gate oxide integrity. The magnetically enhanced RIE (MERIE) system is shown to cause significant gate oxide damage with a pronounced radial dependence. This damage does not occur on wafers etched in the hexode-type RIE system. Experimental work on the MERIE system shows that the presence of the magnetic field during the aluminum overetch and barrier metal etch portion of the process is the primary cause for the observed gate oxide damage. This damage can be minimized by reducing or eliminating the magnetic field during the overetch step.<<ETX>>


Microelectronic device technology. Conference | 1997

Device performance and optimization for 5th- and 6th-generation microprocessors

Bijnan Bandyopadhyay; Jon D. Cheek; Robert Dawson; Michael Duane; Jim Fulford; Mark I. Gardner; Fred N. Hause; Bernard W. K. Ho; Daniel Kadoch; Raymond T. Lee; Ming-Yin Hao; Chuck May; Mark W. Michael; Brad T. Moore; Deepak K. Nayak; John L. Nistler; Dirk Wristers

A family of CMOS processing technologies used to produce AMDs fifth and sixth generation microprocessors (K5 and K6) is described. Some of the issues that arose during the technology development and the transfer to manufacturing are also presented. Transistor performance is compared to literature results and shown to be best in its class.


Archive | 1995

Landing pad technology doubled up as local interconnect and borderless contact for deep sub-half micrometer IC application

Richard J. Huang; Robin W. Cheung; Rajat Rakkhit; Raymond T. Lee


Archive | 1994

Method for eliminating window mask process in the fabrication of a semiconductor wafer when chemical-mechanical polish planarization is used

Raymond T. Lee; Richard K. Klein


Archive | 1999

Nitride disposable spacer to reduce mask count in CMOS transistor formation

Todd P. Lukanc; Raymond T. Lee; Zicheng Gary Ling


Archive | 2000

Reduced masking step CMOS transistor formation using removable amorphous silicon sidewall spacers

Zicheng Gary Ling; Todd P. Lukanc; Raymond T. Lee


Archive | 1997

Method of making static random access memory cell having a trench field plate for increased capacitance

Asim A. Selcuk; Raymond T. Lee


Archive | 1996

Process for deposition of a Ti/TiN cap layer on aluminum metallization and apparatus

Paul R. Besser; Raymond T. Lee; Khanh Tran


Archive | 1997

Forming local interconnects in integrated circuits

Richard K. Klein; Asim A. Selcuk; Nicholas J. Kepler; Craig S. Sander; Christopher A. Spence; Raymond T. Lee; John C. Holst; Stephen C. Horne


Archive | 1997

Method for self-aligning polysilicon gates with field isolation and the resultant structure

Richard K. Klein; Asim A. Selcuk; Nicholas J. Kepler; Craig S. Sander; Christopher A. Spence; Raymond T. Lee; John C. Holst; Stephen C. Horne

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