Rajat Rakkhit

Process induced oxide damage and its implications to device reliability of submicron transistors

Adverse effects of plasma based process steps on the gate oxide and device reliability are discussed. Two aspects of this process induced damage are: (a) antenna effects due to the large areas of conductors connected to the gate in a dense circuit, and (b) progressive deterioration of the gate oxide during processing. It is shown that large areas of conductors can act as antennas and degrade the hot carrier reliability of the transistors due to the process induced damage to the gate oxide. Constant gate current stress experiments show that this degradation is cumulative as the wafers are being processed through the backend of the process flow.<<ETX>>

A comprehensive study of performance and reliability of P, As, and hybrid As/P nLDD junctions for deep-submicron CMOS logic technology

A comprehensive study of P, As, and hybrid As/P nLDD junctions is presented in terms of performance, reliability, and manufacturability for the first time. It is found that As junctions limit the performance of deep submicron devices due to unacceptable hot-carrier reliability, whereas a hybrid junction (light dose P added to medium dose As) dramatically improves hot-carrier reliability while maintaining high performance and manufacturability. For L/sub eff/ of 0.19 /spl mu/m, using this hybrid junction in a manufacturing process, an inverter gate delay of 32 ps, dc hot carrier life time exceeding ten years, and off-state leakage below 30 pA//spl mu/m at 2.9 V have been achieved.

Characterization and optimization of metal etch processes to minimize charging damage to submicron transistor gate oxide

Two metal etch systems are compared in terms of their impacts on submicron transistor gate oxide integrity. The magnetically enhanced RIE (MERIE) system is shown to cause significant gate oxide damage with a pronounced radial dependence. This damage does not occur on wafers etched in the hexode-type RIE system. Experimental work on the MERIE system shows that the presence of the magnetic field during the aluminum overetch and barrier metal etch portion of the process is the primary cause for the observed gate oxide damage. This damage can be minimized by reducing or eliminating the magnetic field during the overetch step.<<ETX>>

Drain-avalanche induced hole injection and generation of interface traps in thin oxide MOS devices

Drain-avalanche-induced hot hole injection in thin oxide MOS devices, used in flash-type EEPROM memory cells, is discussed. A significant amount of acceptor-like interface traps are generated by the injected hot holes, spreading into the channel region. These generated interface traps dramatically alter the channel hot carrier characteristics of the device. This can adversely affect the programmability of a flash memory cell and can cause early window closure. >

An investigation of the time dependence of current degradation in MOS devices

A perturbation technique is used to solve the time-dependent transport equations, giving an accurate picture of the time dependence of hot-carrier-induced degradation in submicrometer MOS devices. The growth of the spatial distribution of both the interface-generated traps and the oxide-trapped charges are incorporated in a two-dimensional model using the effective electron temperature calculations. The calculations and the measurements show a self-limiting behavior of the degradation process. >

A comparison of inverter-type circuit lifetime and quasi-static analysis of NMOSFET lifetime

Performance degradation of inverter-type circuit due to hot carrier injection is investigated. Frequency degradation of the ring oscillators was used as a monitor of the circuit performance for very short gate delay transients. A quasi-static approach was used to correlate the circuit performance with various parameter degradations of discrete NMOSFETs. It is shown that the degradation behavior of the circuit with time is quite different from that of a discrete device. The quasi-static calculations underestimate the degradation in CMOS inverter propagation delay and overestimate the predicted lifetime. The results indicate that created electron traps may be the cause for enhanced degradation.<<ETX>>

An investigation of hot carrier effects in submicron CMOS integrated circuits

Abstract The Static (DC) and Dynamic (AC) Hot Carrier effects on discrete transistors and ring oscillator test structures were reviewed. The relationship between degradations of integrated circuit AC performance and individual device under the DC stress condition was further explained by including 1) effects of hot carrier degradation of PMOS transistors in AC hot carrier modeling; 2) trappy and normal oxide characteristics of PMOS transistors. The models were applied to simulate the CMOS integrated circuit degradation due to hot carrier effects successfully. The simulated AC circuit degradation were verified by long term experimental results.

Impact of boron penetration at the p/sup +/-poly/gate-oxide interface on the device reliability of deep submicron CMOS logic technology

Impact of boron penetration at the p/sup +/-poly/gate-oxide interface is investigated. It is shown that the onset of boron penetration at this interface can not be detected by conventional threshold or flatband voltage shifts of p-channel devices, but it results in significantly lower Q/sub BD/ and Vt instability. Constant current stress in inversion has been found to be most sensitive technique to monitor the onset of boron at the p/sup +/-poly/gate-oxide interface.

A new technique to measure thin oxide thickness in IC manufacturing

A new method to measure thin oxide thickness in CMOS technology is presented. Using a constant Fowler-Nordheim tunneling current through the gate oxide, the tunnel voltage across the oxide has been shown to be linearly proportional to the gate oxide thickness. The proposed tunnel voltage method can detect oxide thickness variation as small as 0.1 /spl Aring/ in product wafers.