Regis Orobtchouk

Incorporation of a Photonic Layer at the Metallizations Levels of a CMOS Circuit

The integration of a photonic layer on a CMOS circuit can be done either by wafer bonding of an SOI photonic circuit or by low temperature fabrication of a photonic layer at the metallization levels

Two different ways for waveguides and optoelectronics components on top of C-MOS

While fabrication of photonic components at the wafer level is a long standing goal of integrated optics, new applications such as optical interconnects are introducing new challenges for waveguides and optoelectronic component fabrication. Indeed, global interconnects are expected to face severe limitations in the near future. To face this problem, optical links on top of a CMOS circuits could be an alternative. The critical points to perform an optical link on a chip are firstly the realization of compact passive optical distribution and secondly the report of optoelectronic components for the sources and detectors. This paper presents two different approaches for the integration of both waveguides and optoelectronic components. In a first total bonding approach, waveguides have been elaborated using classical Silicon On Insulators technology and then reported using molecular bonding on top off Si wafers. The S0I substrate was then chemically etched, after what InP dies were moleculary bonded on top of the waveguides. With this approach, optical components with low loses and a good equilibrium are demonsrated. Using molecular bonding, InP dies were reported with no degradation of the optoelectronic properties of the films. In a second approach, using PECVD silicon nitride or amorphous silicon coupled to PECVD silicon oxide, basic optical components are demonstrated. This low temperature technology is compatible with a microelectronic Back End process, allowing an integration of the waveguides directly on top of CMOS circuits. InP dies can then be bonded on top of the waveguides.

Towards Optical Networks-on-Chip Using CMOS Compatible III-V/SOI Technology

Integrated components for optical networks-on-chip, including III-V microdisk lasers, photodetectors, and wavelength selective circuits, are all demonstrated using a co mplementary metal-oxide-semiconductor (CMOS) compatible III-V/silicon-oninsulator integration technology at 200mm wafer sca le. Keywords—silicon photonics; microdisk lasers and phot odetectors; heterogeneous integration; network-on-chip