Reily M. Jacoby

Multi-level logic minimization using implicit don't cares

An approach is described for the minimization of multilevel logic circuits. A multilevel representation of a block of combinational logic is defined, called a Boolean network. A procedure is then proposed, called ESPRESSOMLD, to transform a given Boolean network into a prime, irredundant, and R-minimal form. This procedure rests on the extension of the notions of primality and irredundancy, previously used only for two-level logic minimization, to combinational multilevel logic circuits. The authors introduce the concept of R-minimality, which implies minimality with respect to cube reshaping, and demonstrate the crucial role played by this concept in multilevel minimization. Theorems are given that prove the correctness of the proposed procedure. Finally, it is shown that prime and irredundant multilevel logic circuits are 100% testable for input and output single-stuck faults, and that these tests are provided as a byproduct of the minimization. >

On properties of algebraic transformation and the multifault testability of multilevel logic

The authors present a number of results exploring the relationship between algebraic transformations for area optimization and the testability of combinational logic circuits. They show that for each multifault in an algebraically factored circuit there is an equivalent multifault in the original circuit, and it is well known that two-level single-output circuits that are single-fault testable are also multifault testable. They also show how these results imply that algebraic factorization may be applied to minimized (and therefore completely single-fault testable) two-level circuits, in order to synthesize area optimized, completely multifault testable circuits. Furthermore, when algebraic factorization is applied to a minimized two-level circuit all tests needed for complete multifault coverage of the synthesized circuit can be derived from the single-fault tests for the original two-level circuit.<<ETX>>

New ATPG techniques for logic optimization

Algorithms are presented for RI (redundancy identification) and RR (redundancy removal). With fault simulation and a backtrack limit of 10, the RI program is able to find a test for all testable faults and identify all the redundant faults in each of the ISCAS benchmark examples. The RR program makes the whole benchmark set 100% testable for single stuck-at faults, and generates the test, in less than 1 CPU hour (SUN4/280). The algorithms were developed for equivalence-based logic optimization applications, which accentuate the role of heuristics in the process of automatic test program generation (ATPG), since this diminishes the role of fault simulation. The authors compare a limited set of results obtained by RR to those of existing logic optimization programs. The results show that in most cases, superior results can be obtained with factors of tens to hundreds speedup in CPU time.<<ETX>>

On properties of algebraic transformations and the synthesis of multifault-irredundant circuits

The authors explore the relationship between algebraic transformations for area optimization and the testability of combinational logic circuits. It is shown that for each multifault in an algebraically factored circuit there is an equivalent multifault in the original circuit. Using this result, it is shown how algebraic factorization may be applied to minimized two-level circuits, to synthesize area-optimized, completely multifault testable multilevel circuits. When a circuit is synthesized using algebraic factorization from a minimized two-level circuit, a reasonably small set of tests that give complete multifault coverage of the synthesized circuit can be derived from the single-fault tests for the original two-level circuit. It is shown that single-fault testability is not an invariant maintained by algebraic transformations, and a simple single-fault irredundant circuit on which the application of algebraic transformations activate a latent multifault, making the resulting algebraically transformed circuit single-fault redundant is presented. >

BOLD: The Boulder Optimal Logic Design system

The BOLD (Boulder-Optimal Logic Design) system is a set of software tools that optimally transform an arbitrary combinational logic description into a standard cell, gate array, or complex CMOS gate technology. The design philosophy and structure of BOLD are summarized, and the various software tools and algorithms that comprise the BOLD system are described. The input to BOLD is either a behavioral circuit description or a Logical Interchange Format (LIF) file. The output is a netlist consisting of gates from a user supplied library or a netlist of CMOS complex gates. The philosophy of BOLD is contrasted with that of other available synthesis programs (most notably MIS and YLE), and the output of each is compared on a small set of examples.<<ETX>>