Subhrajit Bhattacharya

Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications

This paper presents a new method, based on Markov chain analysis, to evaluate the performance of schedules of behavioral specifications. The proposed performance measure is the expected number of clock cycles required by the schedule for a complete execution of the behavioral specification for any distribution of inputs. The measure considers both the repetition of operations (due to loops) and their conditional execution (due to conditional branches). We propose an efficient technique to calculate the metric. We introduce a loop-directed scheduling algorithm (LDS). The algorithm produces schedules such that the expected number of clock cycles, required by the schedule for a complete execution of the behavioral specification, is minimized. Experimental results on several conditional and loop-intensive specifications demonstrate the relevance and effectiveness of both the performancemeasure and the scheduling algorithm.

Clock Period Optimization During Resource Sharing and Assignment

This paper analyzes the effect of resource sharing and assignment on the clock period of the synthesized circuit. We focus on behavioral specifications with mutually exclusive paths, due to the presence of nested conditional branches and loops. It is shown that even when the set of available resources is fixed, different assignments may lead to circuits with significant differences in clock period. We provide a comprehensive analysis of how resource sharing and assignment introduces long paths in the circuit. Based on the analysis, we develop an assignment algorithm which uses a high-level delay estimator to assign operations to a fixed set of available resources so as to minimize the clock period of the resultant circuit. Experimental results on several conditionalintensive designs demonstrate the effectiveness of the assignment algorithm.

Provably correct high-level timing analysis without path sensitization

This paper addresses the problem of true delay estimation during high level design. The existing delay estimation techniques either estimate the topological delay of the circuit which may be pessimistic, or use gate-level timing analysis for calculating the true delay, which may be prohibitively expensive. We show that the paths in the implementation of a behavioral specification can be partitioned into two sets, SP and UP. While the paths in SP can affect the delay of the circuit, the paths in UP cannot. Consequently, the true delay of the resulting circuit can be computed by just measuring the topological delay of the paths in SP, eliminating the need for the computationally intensive process of path sensitization. Experimental results show that high-level true delay estimation can be done very fast, even when gate-level true delay estimation becomes computationally infeasible. The high-level delay estimates are verified by comparing with delay estimates obtained by gate-level timing analysis on the actual implementation.

RT-level transformations for gate-level testability

The authors introduce a technique to transform a given RT-level design into a functionality equivalent, minimized design which is 100% testable under full-scan at the gate level. The proposed optimization technique uses the RT-level structure and exploits the interaction between the control and the data path. The approach maintains the design hierarchy while performing RT-level transformations of initially specified data path, followed by resynthesis of control using do not cares extracted from the data path. Experiments with RTL benchmarks demonstrate the effectiveness of the technique in generating fully testable designs, while consistently reducing area and delay.<<ETX>>

Bridging Behavioral and Register-Transfer Synthesis

This paper considers register-transfer synthesis and optimization from a control-data flowgraph specification. In contrast to scheduling under resource constraints, we derive a register-transfer (RT) description without imposing constraints on resources. The initial RT-level description may seem to have an excessive number of functional units and multiplexors, however it will typically exhibit also high signal reconvergence. We demonstrate with non-trivial benchmark examples that regions of high signal reconvergence offer high resynthesis and optimization potential also at RT-level, producing standard cell realizations that are comparable and competitive with alternate approaches in all aspects: layout area, path delay and gate-level testability. Tradeoffs in resource allocation are examined at RT-level only after optimizing the initial description. The RT-level description we generate serves as a top-level input to OASIS, which expands it to the required data-path components, synthesizes all control specifications, performs test generation and global optimization by redundancy removal and submits the final standard cell netlist for automatic placement and routing.