Reinhold Elferich

Accurate behavioural modelling of power MOSFETs based on device measurements and FE-simulations

Optimization of low voltage power MOSFETs in hard-switching high frequency power converters needs accurate models. This paper deals with a behavioural modelling approach, which employs look-up tables and fitting functions describing the devices characteristics. The required model data can be derived from extensive measurements or alternatively, from finite element (FE) device simulations. Both ways are outlined and compared. A simulation example of a step-down converter shows a typical switching transient and demonstrates the effects covered by the model

Switching loss contributions of synchronous rectifiers in VRM applications

For the synchronous buck converter used in VRM applications, one major contributor to switching losses is reverse recovery. These losses however cannot directly be measured because capacitive current and several other phenomena superimpose the mere reverse recovery. The paper describes how to calculate the capacitive part of the drain current and how to de-embed the channel current out of the total drain current. This can show the size of Q/sub rr/ and reveal effects such as gate bouncing and avalanche breakdown.

Reverse Recovery in High Density Trench MOSFETs with Regard to the Body-Effect

Reverse recovery transients in low voltage trench MOSFETs are investigated by means of finite element simulations. In contrast to the turn-off dynamics of a conventional pn junction diode, the particularity of the body diode turn-off in these MOSFETs is its existing strong gate voltage dependency. This behavior can be explained in theory by the so-called body-effect. Its consequences on the reverse recovery current are analyzed in detailed. A behavioral model for circuit simulators is proposed that accurately describes the relevant phenomena

De-embedding of reverse recovery losses in fast switching VRM applications

For the synchronous buck converter used in VRM applications, one major contributor to switching losses is reverse recovery. These losses however cannot directly be measured because capacitive current and several other phenomena superimpose the mere reverse recovery. The paper describes how calculate the capacitive part of the drain current and how to de-embed the channel current out of the total drain current. This can show the size of Q/sub rr/ and reveal effects such as gate bouncing and avalanche breakdown.

A new load resonant dual-output converter

The resonant dual-output converter (RDOC) is derived from the series-parallel resonant LLC converter by introducing half-wave instead of full-wave rectification. The RDOC regulates two outputs independently using a single power stage. The load range covers any combination including no-load while still maintaining zero voltage switching. This holds for an input voltage range comparable to the conventional LLC converter. The RDOC can further be operated at different secondary voltages per turn in order to meet specific low voltage load requirements. A control structure is outlined that transfers the original error signals into two actuating signals which then separately control frequency and duty cycle.

Measurement Technique for the Static Output Characterisation of High Current Power MOSFETs

A technique for measuring the static output characteristics of high current power MOSFETs is presented. The approach aims at the mitigation of self-heating, which is the source of significant measurement errors in modern commercial curve tracers. The technique is based on the principle of stimulation by means of voltage ramps that allow for fast transient measurements. This however implies the excitation of electric parasitic impedances in the device under test. The paper describes how to control these disturbances and defines the measurement conditions upon which a specified minimum accuracy is guaranteed. Experimental results compare the performance of the measurement method with that of a conventional curve tracer

Static paralleling of power MOSFETs in thermal equilibrium

In automotive applications, sub-systems that used to be driven mechanically or hydraulically increasingly become electrically powered. The required inverters that feed such systems use parallel-connected power MOSFETs to switch hundreds of amperes. This paper investigates the static issues of paralleling MOSFETs, particularly the worst-case scenarios leading to the maximum temperature rise in the devices. A static electro-thermal MOSFET model is employed to describe current sharing and temperature rise for the general case of an arbitrary number of parallel devices. Analytical expressions are obtained to derive the worst-case conditions of the MOSFETs. Thus, designers can benefit from it to guarantee reliable circuit.

PCS layout inductance modeling based on a time domain measurement approach

This paper presents a time domain measurement method to estimate the parasitic inductance of a Printed Circuit Board (PCB) layout. It is based on a lumped element model. The proposed measurement technique is also used for measuring the Equivalent Series Inductance (ESL) of devices such as low ohmic MOSFETs and high current shunt resistors. The PCB layout of a half bridge circuit is characterised as an application example.

Current Sharing of Paralleled Power MOSFETs at PWM Operation

A basic model for static parallel operation of power MOSFETs is extended to include the impact of branch inductances as well as their mismatch on current sharing and on worst-case junction temperature. Assuming moderate temperature ripples, the thermal aspects of paralleling MOSFETs in a typical half-bridge circuit are analysed using a local average approximation method. Regarding PWM operation, equations are derived for the steady state to deduce the worst-case scenario for any number of parallel devices at given parameter spread and operation conditions. In an example, a worst-case is identified by that model, which is then employed in simulations of a more complex electro-thermal SPICE model to further include switching losses. Comparison shows that both of the considered dynamic current-sharing effects may substantially contribute to the peak junction temperatures.

Accurate performance predictions of power MOSFETs in high switching frequency synchronous buck converters for VRM

This paper deals with the modelling and analysis of power MOSFETs for high switching frequency synchronous buck converters targeting voltage regulator module (VRM) applications. The aim is to come up with a modelling approach that enables accurate performance predictions of the power MOSFETs in the switched-circuit. A survey on power MOSFET models is given that provides a basic classification of relevant modelling techniques for circuit simulation. A model is then selected and experimentally validated over a wide range of switching conditions. Also, the loss assessment in a multi-chip module is presented to illustrate the use of a method for comprehensive quantification of loss mechanisms. Overall, the modelling approach helps establish roadmap targets for future device and circuit technology developments.