Toni Lopez

Accurate behavioural modelling of power MOSFETs based on device measurements and FE-simulations

Optimization of low voltage power MOSFETs in hard-switching high frequency power converters needs accurate models. This paper deals with a behavioural modelling approach, which employs look-up tables and fitting functions describing the devices characteristics. The required model data can be derived from extensive measurements or alternatively, from finite element (FE) device simulations. Both ways are outlined and compared. A simulation example of a step-down converter shows a typical switching transient and demonstrates the effects covered by the model

Reverse Recovery in High Density Trench MOSFETs with Regard to the Body-Effect

Reverse recovery transients in low voltage trench MOSFETs are investigated by means of finite element simulations. In contrast to the turn-off dynamics of a conventional pn junction diode, the particularity of the body diode turn-off in these MOSFETs is its existing strong gate voltage dependency. This behavior can be explained in theory by the so-called body-effect. Its consequences on the reverse recovery current are analyzed in detailed. A behavioral model for circuit simulators is proposed that accurately describes the relevant phenomena

Power MOSFET Technology Roadmap Toward High Power Density Voltage Regulators for Next-Generation Computer Processors

A synchronous buck converter based multiphase architecture is evaluated to determine whether or not the most widespread voltage regulator (VR) topology can meet the power delivery requirements of next-generation computer processors. The applied analysis methodology relies on accurate device models for circuit simulations, where the power MOSFETs are central due to their primary relevance to power losses. The method is referred to as virtual design loop and aims at optimizing the overall system performance with minimum empirical efforts. This is successfully applied to the development of a power MOSFET technology offering outstanding dynamic and static performance characteristics in the application. From a system perspective, the limits of power density conversion will be explored for this and other emerging technologies that promise to open up a new paradigm in power integration capabilities.

On the modeling of switched capacitor converters with multiple outputs

The internal nodes of switched capacitor converters can be used to provide multiple pulsed width modulated voltages that, in combination with filter inductors, can extend the available dc outputs. Such converter architecture requires models that accurately predict the behaviour of switched capacitor converters operated in current output mode. Based on the well-known output impedance model, a new circuit representation is proposed for converters with multiple current-loaded outputs. A characterization methodology is developed to determine the parameters of said model. Predictions of the new model compare favorably to circuit simulations and experimental measurements.

Design and Roadmap Methodology for Integrated Power Modules in High Switching Frequency Synchronous Buck Voltage Regulators

The proposed methodology encompasses four study phases that address the following key design aspects of integrated power modules (IPM) for voltage regulators: Fundamental switching understanding, determination of compact/accurate loss expressions and derivation of design rules, guidelines and figure of merits for converter optimisation. The applied methods are based on several modelling approaches suitable for the different study phases. The simplified loss model proves to be effective to breakdown the power losses of a state of the art IPM. Analysis of an optimised design leads to the identification of critical circuit and device parameters that may well condition the layout of future technological roadmap targets.

Measurement Technique for the Static Output Characterisation of High Current Power MOSFETs

A technique for measuring the static output characteristics of high current power MOSFETs is presented. The approach aims at the mitigation of self-heating, which is the source of significant measurement errors in modern commercial curve tracers. The technique is based on the principle of stimulation by means of voltage ramps that allow for fast transient measurements. This however implies the excitation of electric parasitic impedances in the device under test. The paper describes how to control these disturbances and defines the measurement conditions upon which a specified minimum accuracy is guaranteed. Experimental results compare the performance of the measurement method with that of a conventional curve tracer

Static paralleling of power MOSFETs in thermal equilibrium

In automotive applications, sub-systems that used to be driven mechanically or hydraulically increasingly become electrically powered. The required inverters that feed such systems use parallel-connected power MOSFETs to switch hundreds of amperes. This paper investigates the static issues of paralleling MOSFETs, particularly the worst-case scenarios leading to the maximum temperature rise in the devices. A static electro-thermal MOSFET model is employed to describe current sharing and temperature rise for the general case of an arbitrary number of parallel devices. Analytical expressions are obtained to derive the worst-case conditions of the MOSFETs. Thus, designers can benefit from it to guarantee reliable circuit.

PCS layout inductance modeling based on a time domain measurement approach

This paper presents a time domain measurement method to estimate the parasitic inductance of a Printed Circuit Board (PCB) layout. It is based on a lumped element model. The proposed measurement technique is also used for measuring the Equivalent Series Inductance (ESL) of devices such as low ohmic MOSFETs and high current shunt resistors. The PCB layout of a half bridge circuit is characterised as an application example.

Current Sharing of Paralleled Power MOSFETs at PWM Operation

A basic model for static parallel operation of power MOSFETs is extended to include the impact of branch inductances as well as their mismatch on current sharing and on worst-case junction temperature. Assuming moderate temperature ripples, the thermal aspects of paralleling MOSFETs in a typical half-bridge circuit are analysed using a local average approximation method. Regarding PWM operation, equations are derived for the steady state to deduce the worst-case scenario for any number of parallel devices at given parameter spread and operation conditions. In an example, a worst-case is identified by that model, which is then employed in simulations of a more complex electro-thermal SPICE model to further include switching losses. Comparison shows that both of the considered dynamic current-sharing effects may substantially contribute to the peak junction temperatures.

On the impedance modeling of switched capacitor converters with arbitrary output nodes

Demand for high power density and miniaturization are pushing the application limits of Switched Capacitor Converters (SCCs) to new areas. Their benefit has up to now been used only in low power application ICs such as memories, or mobile phone backlighting where efficiency is not critical and magnetic components are not available. Recently, research in SCCs is demonstrating that their benefits can be extended to high power density systems, achieving efficiency levels comparable to classical inductive SMPS. These new concepts consider advanced control schemes or hybrid combinations of SCCs and inductive switching, and require better understandings of the SCC and its appropriate models. This work presents a new methodology to model hybrid combinations of SCCs and inductors. The well-known vector charge flow analysis for Switched Capacitor Converters is reviewed and extended in order to accurately model the behavior of a SCC when any of the internal nodes is loaded and controlled by Pulse-Width-Modulation. Results of the analysis compare favorably to behavioral simulations.