Reinhold Gaertner

Do we expect ESD failures in an EPA designed according to international standards? The need for a process related risk analysis

ESD failures can occur in ESD protected areas that are designed according to the latest ESD standards like ANSI S20.20 or IEC 61340-5-1. The root cause for the failures can normally only be found by a detailed analysis of the whole production flow. This paper shows what hazards for ESD damages can occur in a typical process flow of a typical PCB manufacturing line, how the risk is going to be analyzed, and how it can be minimized. This method will be explained with some examples from the field.

Experience in HBM ESD testing of high pin count devices

HBM ESD sensitivity testing of high pin count devices is a challenge for current testers and the standardized test procedure. Alternative HBM test procedures are described for the test of devices with fewer tester channels than device pins. Experimental results for the ldquoSplit-IOrdquo test method are presented and the risks of divergent results are discussed.

Using CC-TLP to get a CDM robustness value

Charged Device Model (CDM) like stress represents the highest ESD risk during handling of single devices. Today air discharge compromises repeatability of CDM tests of products in a package. The paper demonstrates that the repeatable Capacitive Coupled TLP (CC-TLP) reproduces CDM failure signatures at both package and wafer level. Data will be shown to compare the stress failing level and the failure locations on the chip.

ESD concerns in sawing wafers with discrete semiconductor devices

Wafers with discrete semiconductor devices are sawn without CO2 bubbling. On one hand, there are claims that wafer sawing process using Dl-water without CO2 bubbling is not the state of the art process. On the other hand, there is a major blocking point for the introduction of CO2 bubbling in discrete devices wafer sawing process. Because discrete device wafers have as many as 300K chips on a single 6-inch wafer. Therefore the sawing process requires as long as 2.5 hours to process a wafer. The use of DI water in the sawing process results in severe corrosion issues. Investigations are conducted and the results are presented.semiconductor wafer sawing process

Influence of machine configuration on EOS damage during wafer cleaning process

An investigation was carried out on the charging voltage of deionized (DI) water during wafer cleaning at wafer sawing process, since it was supposed to be the root cause for EOS damages during semiconductor production. The charging voltage was measured using a non-contact electrostatic field meter. It was found that the positioning of the water filter influenced the amount of charging voltage of DI water.