Tilo Brodbeck

Reliability aspects of gate oxide under ESD pulse stress

Power law time-to-breakdown voltage acceleration is investigated down to ultra-thin oxides (1.1 nm) in the ESD regime in inversion and accumulation. Breakdown modes, oxide degradation and device drifts under ESD like stress are discussed as function of the oxide thickness. The consequent impacts on the ESD design window are presented.

CDM tests on interface test chips for the verification of ESD protection concepts

The CDM failure threshold of microelectronic components are determined by the peak value of the discharge current. The requirements of the market, however, are given in terms of potential. In addition, it is not known how the CDM susceptibility of an IC is affected by its core circuitry. This paper introduces an idea how CDM protection concepts can be checked by tests on an interface test chip to guarantee satisfying product qualifications.

Investigation into socketed CDM (SDM) tester parasitics

The ESD Association standards working group 5.3.2 is analyzing the procedure and stress that is applied to a device under test (DUT) using a socketed discharge model (SDM) test system, formerly referred to as socketed CDM. Our final goal is to define an SDM tester specification that will guarantee test result reproducibility across different test equipment. This paper investigates the effect of tester background parasitics on the discharge current waveforms of an SDM tester. Characteristic waveforms were studied and SDM testing was performed on actual devices. It is shown that SDM tester parasitics determine the stress applied to the DUT. This directly affects the SDM failure threshold voltage levels and may lead to miscorrelation and nonreproducibility of test results across different SDM test systems. This paper empirically determines the relative contributions of the various tester parasitics to the total stress applied to the DUT. Our investigations indicate that the tester provides 10 to 20 pF parasitic capacitance discharge into each pin of the device. Tester background parasitic elements play such an important role in the SDM discharge event that correlation between test systems built by different manufacturers is unlikely without completely duplicating a particular tester.

Experience in HBM ESD testing of high pin count devices

HBM ESD sensitivity testing of high pin count devices is a challenge for current testers and the standardized test procedure. Alternative HBM test procedures are described for the test of devices with fewer tester channels than device pins. Experimental results for the ldquoSplit-IOrdquo test method are presented and the risks of divergent results are discussed.

Do ESD fails in systems correlate with IC ESD robustness

Abstract Integrated circuits (ICs) are qualified for their electrostatic discharge (ESD) robustness according to the well-known IC ESD standards Human Body Model, Machine Model, and Charged Device Model in order to guarantee safe handling in ESD protected areas. For electronic systems like mobile phones which are in direct use by consumers, certain robustness against system level ESD is demanded, too. As the ESD test methods of device and system level stress are completely different (waveforms, stress application, operating condition of the DUT, etc.), correlations between models of both worlds are difficult to establish. Therefore, the system vendors more and more demand a specified ESD robustness for devices (ICs) according to an ESD system level standard. Testing ICs to a system level ESD standard requires careful considerations; first ideas are summarized in the new Standard Practice “Human Metal Model” of the ESDA/ANSI. However, the approach of deriving system ESD robustness from IC robustness is currently too much simplified and bears severe potential risks. Nevertheless, there are methodologies and approaches to use IC ESD characterization for defining ESD protection concepts for systems. Appropriate high-current characterization of ICs can be the cornerstone for a successfully optimized system ESD protection.

Triggering of Transient Latch-up by System-Level ESD

This paper investigates the influences of temperature and the trigger parameters (width and rise time) on the threshold of transient latch-up (TLU). It is shown that temperature is a much more critical parameter than transient trigger parameters. For high discharge currents which are typical for system-level surges as, e.g., seen in cable discharge events, even very short trigger pulses can cause TLU.

Influence of the device package on the results of charged device model (CDM) tests — consequences for tester characterization and test procedure☆

Abstract The results of charged device model (CDM) device level tests — opposite to socketed device model (SDM) — are strongly influenced by the device packages. An investigation on different types of devices (technology and package) shows that the CDM withstand voltage depends on the peak current of the discharge current waveform and not on the charge which is stored on the device after charging. This information has important consequences on tester characterization and the test procedure. Moreover, peak current investigation gives a chance to extrapolate CDM results from one specific package to other packages and even perhaps for SDM/CDM correlation.