Wolfgang Stadler

Reliability aspects of gate oxide under ESD pulse stress

Power law time-to-breakdown voltage acceleration is investigated down to ultra-thin oxides (1.1 nm) in the ESD regime in inversion and accumulation. Breakdown modes, oxide degradation and device drifts under ESD like stress are discussed as function of the oxide thickness. The consequent impacts on the ESD design window are presented.

Bipolar model extension for MOS transistors considering gate coupling effects in the HBM ESD domain

The compact model for NMOS transistors combines both the high-current bipolar mode and the MOS mode, considering the modulation of the current gain /spl beta/ and the gate coupling effects. For the studied 0.35 /spl mu/m-CMOS device, measurement and simulation correlate very well with respect to layout variations, fulfilling a prerequisite for the simulation guided synthesis and optimization of protection structures and schemes. The open model interface also allows the use of existing proprietary MOS-models.

Characterization and modeling of transient device behavior under CDM ESD stress

Device physical effects that strongly influence the transient behavior during very fast, high current pulses are discussed. The effects are studied by experimental characterization and device simulation. The dependence on the technology (deep-sub-micron, smart-power/high-voltage) is considered as well. Compact models for CDM circuit simulation are developed.

Development strategy for TLU-robust products

Detailed transient latch-up (TLU) analyses of external test structures show that a DC trigger does not necessarily reflect worst case conditions. Furthermore, the classical guard ring latch-up protection approach fails for transient trigger. In this contribution, design recommendations for TLU-safe designs are presented. The knowledge about the perturbation environment and an appropriate design are essential for a TLU-robust product.

CDM tests on interface test chips for the verification of ESD protection concepts

The CDM failure threshold of microelectronic components are determined by the peak value of the discharge current. The requirements of the market, however, are given in terms of potential. In addition, it is not known how the CDM susceptibility of an IC is affected by its core circuitry. This paper introduces an idea how CDM protection concepts can be checked by tests on an interface test chip to guarantee satisfying product qualifications.

Transient latch-up: experimental analysis and device simulation

A set-up consisting of at least one pulse generator with baseline functionality was used for Transient Latch-up (TLU) investigations. Dependencies of the TLU sensitivity of test structures on the pulse width and the rise time have been analyzed. Device simulation could reproduce the tendencies and reveals the root cause for the dependencies. In a bipolar product, which is immune against static latch-up, transient latch-up could be triggered, showing clearly the importance of a TLU characterization and the capability of the set-up.

Capacitively coupled transmission line pulsing cc-TLP: a traceable and reproducible stress method in the CDM-domain

This paper describes a new test method called Capacitively Coupled Transmission Line Pulsing cc-TLP. It is applied to different test circuits which were mounted on specially designed package emulators with a defined background capacitance. The test results are compared with the ESD thresholds obtained by CDM tests. The CC-TLP results correlate well with the CDM data.

Do ESD fails in systems correlate with IC ESD robustness

Abstract Integrated circuits (ICs) are qualified for their electrostatic discharge (ESD) robustness according to the well-known IC ESD standards Human Body Model, Machine Model, and Charged Device Model in order to guarantee safe handling in ESD protected areas. For electronic systems like mobile phones which are in direct use by consumers, certain robustness against system level ESD is demanded, too. As the ESD test methods of device and system level stress are completely different (waveforms, stress application, operating condition of the DUT, etc.), correlations between models of both worlds are difficult to establish. Therefore, the system vendors more and more demand a specified ESD robustness for devices (ICs) according to an ESD system level standard. Testing ICs to a system level ESD standard requires careful considerations; first ideas are summarized in the new Standard Practice “Human Metal Model” of the ESDA/ANSI. However, the approach of deriving system ESD robustness from IC robustness is currently too much simplified and bears severe potential risks. Nevertheless, there are methodologies and approaches to use IC ESD characterization for defining ESD protection concepts for systems. Appropriate high-current characterization of ICs can be the cornerstone for a successfully optimized system ESD protection.

External (transient) latchup phenomenon investigated by optical mapping (TIM) technique

Substrate current distribution as trigger for external latchup (LU) and transient latchup (TLU) is detected successfully by means of optical transient interferometric mapping (TIM) technique. The substrate current flow is studied on transient base and for various guard-ring configurations. TIM uncovers proximity effects causing substrate current crowding which are important for the definition of LU protection concepts.

Test circuits for fast and reliable assessment of CDM robustness of I/O stages

CDM hardening during the development of technology, devices, libraries and finally products differs significantly from the process well-established for HBM. This paper introduces a method on the basis of specialized CDM test structures including protection elements and sensitive monitor elements. These test structures mimic typical CDM-sensitive circuits found by physical failure analysis over the years. Manufactured in five different technologies, structures were assembled in both a regular package and a new package emulator. CDM stress tests, vf-TLP tests, backside laser interferometry, device simulation, and failure analysis lead to new insights in the complex interdependencies during CDM and underline the need of CDM-specific test structures.