Rémi Robutel

Design and Implementation of Integrated Common Mode Capacitors for SiC-JFET Inverters

This paper deals with the issue of electromagnetic interference (EMI) in SiC-JFET inverter power modules, and proposes a solution to limit conducted emissions at high frequencies. SiC-JFET inverters can achieve very fast switching, thereby reducing commutation losses, at the cost of a high level of EMI. In order to limit conducted EMI emissions, it is proposed to integrate small-value common-mode (CM) capacitors, directly into the power module. High-frequency noise, which is usually difficult to filter, is then contained within the module, thus keeping it far from the external network. This approach is in line with the current trend toward the integration of various functions (such as protection, sensors or drivers) around power devices in modern power modules. To demonstrate this concept, the resulting CM noise was investigated, and compared with a standard configuration. Simulations were used to design the integrated capacitors, and measurements were carried out on an experimental SiC-JFET half-bridge structure. A significant reduction was achieved in the experimentally observed CM conducted emissions, with a very minor influence on the switching waveforms, losses, and overall size of the system. The benefits and limitations of this design are discussed for the case of mid-power range inverters for aircraft applications.

Integrated common mode capacitors for SiC JFET inverters

SiC-JFET based inverters can achieve very fast switching, hence reducing the commutation losses, at the cost of increased Electro-Magnetic Interferences (EMI). To keep the EMI conducted emissions within reasonable limits, we propose to integrate some small-values capacitors directly into the power module. Common Mode (CM) is investigated and compared with a standard configuration. The high frequency noise, which is usually difficult to filter, is contained in a close loop with the switching source, and far from the network. To demonstrate this concept, simulations are used as well as experiments on a SiC-JFET half-bridge structure. Benefits and limitations are investigated in the case of mid-power range inverters for aircraft applications.

High Temperature Ageing of Fe-based Nanocrystalline Ribbons

The impact of long-term high-temperature stress on nanocrystalline Finemet materials is measured by keeping samples at 200 °C for 1300 hours. The standard industrialized, high permeability Finemet materials as well as the recently available low permeability Finemet materials are investigated. Characterizations are performed at different frequencies, temperatures and magnetic field excitations on both aged and non-aged samples. Their complex permeability is also measured during the ageing test. Irreversible changes are pointed out on permeability, coercive field and magnetic flux density at saturation. Regarding the design considerations for high temperature power electronics, the suitability of these materials is demonstrated but an ageing effect has to be considered nonetheless. The presented data can be extrapolated to several thousand hours at 200 °C using the presented empiric ageing law.

Sintered-Silver Bonding of High-Temperature Piezoelectric Ceramic Sensors

Silver sintering is used to bond five components together in order to form a piezoelectric sensor. A description is provided of the preparation of these components, and of the manufacturing steps, which are carried out at a low temperature (280 °C). The resulting sensor assemblies are then characterized: Cross-sectional views show that the silver layer has a very dense structure, with less than 1% porosity, although further focused ion beam investigations show that this porosity is closer to 15%. The shear strength is approximately 30 MPa. Youngs modulus of the silver bondline is measured using nanoindentation, and is found to be comparable to that of bulk silver (56.6 GPa). Finally, a silver-sintered sensor is compared to a sensor bonded using conventional techniques, showing that an improvement in sensitivity by a factor of more than 3 is achieved.

Electro-Thermal Behaviour of a SiC JFET Stressed by Lightning Induced Over-Voltages

JFET are experimentally stressed to provide data for modelling, inverter and driver design. The experxadimental set-up is described. A surge generator is built and a SiC JFET is stressed. During the stress, a temperature estimation is done at increasing time steps, in order to obtain the full thermal response versus time.