Renato Fernandes Hentschke

Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing

This paper presents a quadratic placement algorithm to be applied for 3D circuits. We formulate the 3D problem to control the area balance and the number of 3D-Vias between tiers. We introduce the z-Cell Shifting operation in order to control the area balance. We also define a new operation for the refinement of the solution called 3D Iterative Refinement, that has a control statement to avoid excessive number of 3D-Vias in order to keep the feasibility of our placement solution. After quadratic placement, we move to the placement legalization that is based on min-cost max flow and Simulated Annealing. For detailed placement refinement, we apply Simulated Annealing without cell migration between tiers. Experimental results show that our placement flow targeting one tier is comparable to academic tools such as FastPlace, Capo and Dragon in wire length and running time when targeting a single tier. On multiple tiers, we can reduce the average wire length from 7% (2 tiers) to 32% (5 tiers) and worst wire length by 26% (2 tiers) to 52% (5 tiers). The number of 3D-Vias obtained is feasible since the area overhead introduced is always below 10%.

3D-Vias Aware Quadratic Placement for 3D VLSI Circuits

This paper presents a cell placement algorithm for 3D-circuits. Compared to existing approaches, our placer has a number of new features that delivers more realism and improved wire length. First, the algorithm balances the tier utilization considering the effect of 3D-vias within two possible integration strategies: face-to-face and face-to-back. 3D-vias count is limited to an upper bound, that is sensible to the area of the 3D-via. Within the upper bound, the placer is free to add more 3D-vias, fact that delivers an improved wire length, as demonstrated experimentally in the paper. Our algorithm is based on a true 3D quadratic placement engine with a 3D cell shifting method to spread the cells out and on an iterative refinement step that improves wire length. Experimental results show that our algorithm can improve the wire length compared to a 2D solution provided by the FastPlace algorithm from 15% up to 27% in average.

Maze routing steiner trees with effective critical sink optimization

This paper addresses the problem of generating good topologies of rectilinear Steiner trees using path search algorithms. We present AMAZE, a fast maze router based algorithm that employs selected techniques to build optimized steiner trees. A biasing technique proposed for wire length improvement produces trees that are within 2% from optimal topologies in average. By introducing a sharing factor and a path-length factor we show how to trade-off wire length for delay. Our experimental results show that AMAZE is more effective to optimize delay to critical sinks than state of the art heuristics for Steiner trees, such as AHHK (from 26% to 40%) and P-Trees (from 1% to 30%) while keeping the properties of a routing algorithm. We also analyzed the ability of AMAZE to handle blockages and verified experimentally that AMAZE produces tree with better delay to the critical sinks than P-Trees from 6% (5 pin nets) to 21% (9 pin nets). An important motivation for this work lies in the fact that, due to its acceptable run time and quality of results, AMAZE can be used for estimation in the early stages as well as for actual routing, thereby improving the convergence and timing closure of the design significantly.

Maze Routing Steiner Trees With Delay Versus Wire Length Tradeoff

In this paper, we address the problem of generating good topologies of rectilinear Steiner trees using path search algorithms. Various techniques have been applied in order to achieve acceptable run times on a maze router that builds Steiner trees. A biasing technique proposed for wire length improvement, produces trees that are within 2% from optimal topologies in average. By introducing a sharing factor and a path-length factor we show how to trade-off wire length for delay. Experimental results show that our algorithm generates topologies with better delay compared to state of the art heuristics for Steiner trees, such as AHHK (from 26% to 40%) and P-Trees (from 1% to 30% and from 6% to 21% in the presence of blockages) while keeping the properties of a routing algorithm. An important motivation for this work lies in the fact that it can be used for estimation in the early stages as well as for actual routing, thereby improving the convergence and timing closure of the design significantly. We also provide some valuable theoretical background and insights on delay optimization and on how it relates to our maze router implementation.

A 3D-Via Legalization Algorithm for 3D VLSI Circuits and its Impact on Wire Length

This paper studies the 3D-via placement problem for 3D circuits. We model the problem in such a way that 3D-vias are assigned to layers between the circuit tiers. The placement problem consists of placing the 3D-vias with no overlap with other 3D-vias in the same layer. Positions inside the net bounding box are preferred and wire length minimization is used as target function. We present a heuristic based on the Tetris legalization approach for the 3D-via legalization. Our experimental results show that the algorithm could accommodate the 3D-vias in such a way that wire length overhead is close to zero in easy instances and still very low for harder instances (in most of the cases it is less than 0.1% and it is less than 5% in all cases). Compared to an existing approach, it obtains similar results with orders of magnitude advantage on run time.

An Algorithm for I/O Partitioning Targeting 3D Circuits and Its Impact on 3D-Vias

In this paper we discuss the migration of a 2D netlist with pre-placed I/Os to 3D circuits. For that, we present an algorithm to perform the partitioning of the I/O pins into various tiers targeting at I/O balancing and 3D-vias minimization. We formulate the netlist migration constrained with respect to the preservation of some original netlist properties. The I/O partitioning algorithm is based on the logic distance between I/Os. Since there is no literature on I/O partitioning for 3D circuits we compared our algorithm with two simplistic approaches that targeted balance and min-cut respectively. Experimental results show that our algorithm can reduce the number of 3D-vias compared to both algorithms, while balance is kept close to optimal. Most importantly, we showed that performing I/O partitioning separately we can reduce the number of 3D-vias even more than existing solutions in the literature for the netlist partitioning. Additionally, we studied the area impact of the 3D-vias resulted from the three algorithms targeting two different technologies for 3D circuits. We observed that especially in the bulk based technologies the 3D-via penalty is huge, favoring our algorithm

An Algorithm for I/O Pins Partitioning Targeting 3D VLSI Integrated Circuits

This paper shows the impact of I/O pins partitioning on 3D circuits. Previous works on 3D placement did not focused on the I/Os partitioning and placement. This work presents an algorithm based on the logic proximity of the pins, which is used as weights to a min-cut partitioning. Our method calculates the area of the tiers while placing the I/Os on the boundaries. Initial whitespaces and aspect ratio as well as the initial pins orientation and ordering are preserved. The method is compared to two other simplistic methods for pins partitioning. Our experimental results show that our method is efficient since it can balance the I/O pins distribution in the various tiers while leading to improvements in wire length and number of 3D vias.

Improving simulated annealing placement by applying random and greedy mixed perturbations [IC layout]

This paper presents an improvement to placement using simulated annealing by applying a mix of greedy perturbations with the traditional random perturbations. The used greedy movements are based on a force-directed technique focused on wire length optimization. By analyzing cost curves related to running time, it is possible to see that our technique can converge faster than with any isolated technique. The experiment results show that our mixed perturbation schema outperforms the Timberwolf (C. Sechen et al., IEEE J. Solid-State Ccts., vol. SSC-20, 1995) random perturbation approach by 13.18% (wire length) and 21.36% (maximum wire congestion) in the best case.

Cell placement on graphics processing units

Graphics Processing Units (GPUs) can be viewed as stream processors and, therefore, can be applied to improve the performance of data-parallel algorithms. GPUs can beat CPUs in most stream-like algorithms and have been successfully applied to solve problem in areas such as biology, audio and image processing, database queries and others. This paper presents a VLSI cell placement tool running on a GPU in order to show the viability of applying graphics hardware to improve the performance of CAD tools. Our results show that GPU versions of linear algebra algorithms run 3x or more faster than CPU versions.

Plic-Plac: a novel constructive algorithm for placement

The increasing importance of meta-heuristics, demands solutions to their main drawback, the CPU time required. Initial placement is done by constructive placement algorithms such as Random and Quadratic placement. This article presents a new algorithm for constructive placement, with a CPU time comparable to random placement but with improvement of 39,5% in Wire Length and a 48,8% improvement in wire congestion to the random technique.