Sandro Sawicki

A cells and I/O pins partitioning refinement algorithm for 3D VLSI circuits

Partitioning algorithms are responsible for the assignment of the random logic blocks and ip blocks into the different tiers of a 3D design. Cells partitioning also helps to reduce the complexity of the next steps of the physical synthesis (placement and routing). In spite of the importance of cells partitioning for the automatic synthesis of 3D designs it has been performed in the same way as in 2D designs. Graph partitioning algorithms are used to divide the cells into the different tiers without accounting for any tier location information. Due to the single dimensional alignment of the tiers connections between the bottom and top tiers have to go through all the tiers in between, e. g., in a design with five tiers a connection between the top and the bottom tiers would require four 3D-vias. 3D vias are costly in terms of routing resources and delay and therefore must be minimized. This paper presents a methodology for reducing the number of 3D-vias during the circuit partitioning step by avoiding connections between non-adjacent tiers. Our algorithm minimizes the total number of 3D-vias while respecting area balance, number of tiers and I/O pins balance. Experimental results show that the number of 3D-vias was reduced by 19%, 17%, 12% and 16% when benchmark circuits were designed using two, three, four and five tires.

An Algorithm for I/O Partitioning Targeting 3D Circuits and Its Impact on 3D-Vias

In this paper we discuss the migration of a 2D netlist with pre-placed I/Os to 3D circuits. For that, we present an algorithm to perform the partitioning of the I/O pins into various tiers targeting at I/O balancing and 3D-vias minimization. We formulate the netlist migration constrained with respect to the preservation of some original netlist properties. The I/O partitioning algorithm is based on the logic distance between I/Os. Since there is no literature on I/O partitioning for 3D circuits we compared our algorithm with two simplistic approaches that targeted balance and min-cut respectively. Experimental results show that our algorithm can reduce the number of 3D-vias compared to both algorithms, while balance is kept close to optimal. Most importantly, we showed that performing I/O partitioning separately we can reduce the number of 3D-vias even more than existing solutions in the literature for the netlist partitioning. Additionally, we studied the area impact of the 3D-vias resulted from the three algorithms targeting two different technologies for 3D circuits. We observed that especially in the bulk based technologies the 3D-via penalty is huge, favoring our algorithm

An Algorithm for I/O Pins Partitioning Targeting 3D VLSI Integrated Circuits

This paper shows the impact of I/O pins partitioning on 3D circuits. Previous works on 3D placement did not focused on the I/Os partitioning and placement. This work presents an algorithm based on the logic proximity of the pins, which is used as weights to a min-cut partitioning. Our method calculates the area of the tiers while placing the I/Os on the boundaries. Initial whitespaces and aspect ratio as well as the initial pins orientation and ordering are preserved. The method is compared to two other simplistic methods for pins partitioning. Our experimental results show that our method is efficient since it can balance the I/O pins distribution in the various tiers while leading to improvements in wire length and number of 3D vias.

Collaborative design using a shared object spaces infrastructure

A collaborative design system strongly depends on the chosen collaboration methodology, as well as on its technological infrastructure. This article describes the implementation of collaborative service based on shared object spaces as technological infrastructure and its methodology is based on pair programming. This service is to be incorporated in a distributed collaborative environment called Cave. The collaboration service implementation presented in this work allows collaboration among designers through a data depository. This service is validated with a diagram editor that is used as case study.

A Method for I/O Pins Partitioning Targeting 3D VLSI Circuits

This paper presents an algorithm for I/O pins partitioning and placement targeting 3D circuits. The method starts from a standard 2D placement of the pins around a flat rectangle and outputs a 3D representation of the circuit composed of a set of tiers and pins placed at the four sides of the resulting cube. The proposed algorithm targets a balanced distribution of the I/Os that is required both for accommodating the pins evenly as well as to serve as an starting point for cell placement algorithms that are initially guided by I/O’s locations, such as analytical placers. Moreover, the I/O partitioning tries to set pins in such a way the it allows the cell placer to reach a reduced number of 3D-Vias. The method works in two phases: first the I/O partitioning considering the logic distances as weights; second, fix the I/Os and perform partitioning of the cells. The experimental results show the effectiveness of the approach on balance and number of 3D-Vias compared to simplistic methods for I/O partitioning, including traditional min-cut algorithms. Since our method contains the information of the whole circuit compressed in a small graph, it could actually improve the partitioning algorithm at the expense of more CPU time. Additional experiments demonstrated that the method could be adapted to further reduce the number of 3D-Vias if the I/O pin balance constraint can be relaxed.

Unbalacing the I/O Pins Partitioning for Minimizing Inter-Tier Vias in 3D VLSI Circuits

The 3D Circuit technologies appear as a possible solution for interconnect optimization. For most of the 3D technologies, the 3D-Vias represent a very complex issue because of large pitch requirements and heavy usage of routing constraints. New algorithms and CAD methods must be developed in order to take advantage of the high integration of elements and potentially shorter wire lengths while keeping track of the 3D-Vias. One of the CAD problems, addressed by this paper, is the partition and placement of the I/O pins of a block into sub-blocks that are partitioned into the circuit tiers. In this paper, we extend our previous work in the field to trade-off the I/O pins balance for improved cut. The new version of our partitioning algorithm outperformed the widely used hMetis algorithm in number of 3D-Vias from 2% to 10% (depending on the I/O pins balance), while the standard deviation of the number of I/Os increased. We also observed that the maximum number of 3D-Vias between pairs of adjacent tiers dropped by 14% (in the best case) with the I/O pin unbalance.