Paris Kitsos

Hardware implementation of the RC4 stream cipher

In this paper, an efficient hardware implementation of the RC4 stream-cipher is proposed. In contrary to previous designs, which support only fixed length key, the proposed implementation integrates in the same hardware module an 8-bit up to 128-bit key length capability. Independently of the key length, the proposed VLSI implementation achieves a data throughput up to 22 Mbytes/sec in a maximum frequency of 64 MHz. The whole design was captured by using VHDL language and a FPGA device was used for the hardware implementation of the architecture. A detailed analysis, in terms of performance, and covered area is shown.

An efficient reconfigurable multiplier architecture for Galois field GF(2m)

This paper describes an efficient architecture of a reconfigurable bit-serial polynomial basis multiplier for Galois field GFð2 m Þ; where 1 , m # M: The value m; of the irreducible polynomial degree, can be changed and so, can be configured and programmed. The value of M determines the maximum size that the multiplier can support. The advantages of the proposed architecture are (i) the high order of flexibility, which allows an easy configuration for different field sizes, and (ii) the low hardware complexity, which results in small area. By using the gated clock technique, significant reduction of the total multiplier power consumption is achieved. q 2003 Elsevier Ltd. All rights reserved.

Comparison of the hardware architectures and FPGA implementations of stream ciphers

In this paper, the hardware implementations of five representative stream ciphers are compared in terms of performance and consumed area. The ciphers used for the comparison are the A5/1, W7, E0, RC4 and Helix. The first three ones have been used for the security part of well-known standards. The Helix cipher is a recently introduced fast, word oriented, stream cipher. The W7 algorithm has been recently proposed as a more trustworthy solution for GSM, due to the security problems that occurred concerning the A5/1 strength. The designs were coded using the VHDL language. For the hardware implementation of the designs, an FPGA device was used. The implementation results illustrate the hardware performance of each cipher in terms of throughput-to-area ratio. This ratio equals: 5.88 for the A5/1, 1.26 for the W7, 0.21 for the E0, 2.45 for the Helix and 0.86 for the RC4.

An efficient implementation of the digital signature algorithm

Digital signature schemes are commonly used as primitives in cryptographic protocols that provide other services including entity authentication, authenticated key transport, and authenticated key agreement. A VLSI implementation of the digital signature scheme is proposed in this paper, for efficient usage in any cryptographic protocol. This architecture is based on secure hash function and the 512-bit RSA cryptographic algorithm. The whole design was captured by using VHDL language and a FPGA device was used for the hardware implementation of the architecture. A method to reduce the switching activity of the overall design is introduced. The proposed VLSI implementation of the digital signature scheme achieves a data throughput up to 32 kbit/sec.

Random number generator architecture and VLSI implementation

Security protocols and encryption algorithms are basically based on random number generators. In this paper, a new random number generator architecture is introduced. The produced number word length is equal to 160 bits. The philosophy of the architecture relies on the usage of the SHA hash function. The offered security strength of this hash function ensures the unpredictability of the produced number. Additionally, an efficient VLSI implementation for FPGA devices of the proposed system is described. The proposed architecture is a flexible solution in applications where the original physical sources of random number generators, such as electrical noise, are not available or at least not convenient. This architecture can also be used in any cryptographic algorithm and encryption/decryption system with high-speed performance.

Security in RFID and Sensor Networks

In the past several years, there has been an increasing trend in the use of Radio Frequency Identification (RFID) and Wireless Sensor Networks (WSNs) as well as in the integration of both systems due to their complementary nature, flexible combination, and the demand for ubiquitous computing. As always, adequate security remains one of the open areas of concern before wide deployment of RFID and WSNs can be achieved. Security in RFID and Sensor Networks is the first book to offer a comprehensive discussion on the security challenges and solutions in RFID, WSNs, and integrated RFID & WSNs, providing an essential reference for those who regularly interface with these versatile technologies.Exposes Security RisksThe book begins with a discussion of current security issues that threaten the effective use of RFID technology. The contributors examine multi-tag systems, relay attacks, authentication protocols, lightweight cryptography, and host of other topics related to RFID safety. The book then shifts the focus to WSNs, beginning with a background in sensor network security before moving on to survey intrusion detection, malicious node detection, jamming, and other issues of concern to WSNs and their myriad of applications. Offers Viable SolutionsIn each chapter, the contributors propose effective solutions to the plethora of security challenges that confront users, offering practical examples to aid in intuitive understanding. The last part of the book reviews the security problems inherent in integrated RFID & WSNs. The book ends with a glimpse of the future possibilities in these burgeoning technologies and provides recommendations for the proactive design of secure wireless embedded systems.

A reconfigurable linear feedback shift register (LFSR) for the Bluetooth system

The Bluetooth Encryption/Decryption algorithm demands Linear Feedback Shift Registers (LFSRs) in order to reduce the length of the encryption key. A typical implementation needs sixteen different LFSRs. In this paper a low power 128-bit LFSR for efficient use in portable Bluetooth telecommunication systems is proposed. The new LFSR design techniques can be also useful in any reconfigurable LFSR. Two methods to reduce the conventional LFSR switching activity are introduced. Up to 110% LFSR power consumption reduction was achieved by using the clock-gating technique and the Gray code representation. The whole LFSR design was captured by using VHDL language and for synthesis a 0.7 /spl mu/m CMOS standard cell library was used.

64-bit Block ciphers: hardware implementations and comparison analysis

A performance comparison for the 64-bit block cipher (Triple-DES, IDEA, CAST-128, MISTY1, and KHAZAD) FPGA hardware implementations is given in this paper. All these ciphers are under consideration from the ISO/IEC 18033-3 standard in order to provide an international encryption standard for the 64-bit block ciphers. Two basic architectures are implemented for each cipher. For the non-feedback cipher modes, the pipelined technique between the rounds is used, and the achieved throughput ranges from 3.0Gbps for IDEA to 6.9Gbps for Triple-DES. For feedback ciphers modes, the basic iterative architecture is considered and the achieved throughput ranges from 115Mbps for Triple-DES to 462Mbps for KHAZAD. The throughput, throughput per slice, latency, and area requirement results are provided for all the ciphers implementations. Our study is an effort to determine the most suitable algorithm for hardware implementation with FPGA devices.

Exciting FPGA cryptographic Trojans using combinatorial testing

Contemporary hardware design shares many similarities with software development. The injection of malicious functionality (Trojans) in FPGA designs is a realistic threat. Established techniques for testing correctness do not cope well with Trojans, since Trojans are not captured in the system model. Furthermore, a well-designed Trojan activates under rare conditions and can escape detection during testing. Such conditions cannot be exhaustively searched, especially in the case of cryptographic core implementations with hundreds of inputs. In this paper, we explore the applicability of a prominent combinatorial strategy, namely combinatorial testing, for FPGA Trojan detection. We demonstrate that combinatorial testing provides the theoretical guarantees for exciting a Trojan of specific lengths by covering all input combinations. Our findings indicate that combinatorial testing constructs can improve the existing FPGA Trojan detection capabilities by reducing significantly the number of tests needed. Besides the foundations of our approach, we also report on first experiments that indicate its practical use.

An FPGA Implementation of the ZUC Stream Cipher

In this paper a hardware implementation of ZUC stream cipher is presented. ZUC is a stream cipher that forms the heart of the 3GPP confidentiality algorithm 128-EEA3 and the 3GPP integrity algorithm 128-EIA3, offering reliable security services in Long Term Evolution networks (LTE). A detailed hardware implementation is presented in order to reach satisfactory performance results in LTE systems. The design was coded using VHDL language and for the hardware implementation, a XILINX Virtex-5 FPGA was used. Experimental results in terms of performance and hardware resources are presented.