Rex T. Baird

A 2.5-Gb/s Multi-Rate 0.25-

A 0.25-mum CMOS, multi-rate clock and data recovery (CDR) circuit that leverages unique analog/digital boundaries in its phase detector and loop filter to achieve a fully integrated CDR implementation with excellent performance, compact area, and low power dissipation is presented. Key circuit blocks include a phase-to-digital converter that combines a Hogge detector with a continuous-time first-order Sigma-Delta analog-to-digital converter, and a hybrid loop filter that contains an analog feedforward path and digital integrating path. In addition, an all-digital frequency acquisition method that does not require a reference frequency, quadrature phases from the VCO, or a significant amount of high-speed logic is presented. A nice byproduct of the frequency acquisition circuitry is that it also provides an estimate of the bit error rate (BER) experienced by the CDR. The CDR exceeds all SONET performance requirements at 155-, 622-, and 2500-Mb/s as well as Gigabit Ethernet specifications at 1.25 Gb/s. The chip operates with either a 2.5- or 3.3-V supply, consumes a maximum of 197 mA across all data rates, and fits in a 5times5 mm package

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A CDR comprises a Hogge detector and a 1st-order DeltaSigmaADC, and uses a hybrid analog/digital loop filter to enhance integration and allow bandwidth tuning over a wide range of data rates from 155Mb/s to 2.7Gb/s. The CDR exceeds SONET performance at relevant data rates and generates 1.2psrms jitter at 2.5Gb/s