Yunteng Huang

MOSFET-only switched-capacitor circuits in digital CMOS technology

Design techniques are described for the realization of precision high linearity switched-capacitor (SC) stages constructed entirely from MOS transistors. The proposed circuits use the gate-to-channel capacitance of MOSFETs for realizing all capacitors. As a result, they can be fabricated in any inexpensive basic digital CMOS technology, and the chip area occupied by the capacitors can be reduced. A number of different SC stages have been designed and fabricated using the proposed techniques. These included SC amplifiers, gain/loss stages, and data converters. Both the simulations and the experimental results obtained indicate that very high linearity (comparable to that achieved using analog fabrication processes with two poly-Si layers) can be achieved in these circuits using basic CMOS technology.

MOSFET-only switched-capacitor circuits in digital CMOS technologies

Design techniques are described for high-linearity switched-capacitor (SC) stages constructed entirely from MOS transistors. The proposed circuits use the gate-to-channel capacitance of MOSFETs for realizing all capacitors. As a result, they can be fabricated in any inexpensive basic digital CMOS technology, and the chip area occupied by the capacitors is much reduced. A number of different SC stages have been designed and fabricated using the proposed techniques. These included SC amplifiers, gain/loss stages and data converters. Both the simulations and the experimental results obtained indicated that very high linearity can be achieved in these circuits.

Reduced nonlinear distortion in circuits with correlated double sampling

It is shown that in a class of SC circuits using correlated double sampling the harmonic distortion caused by nonlinear op-amps is greatly reduced. Hence, these circuits are very useful in applications such as input stages in high-linearity amplifiers or in delta-sigma converters.

A high-frequency track-and-hold stage with offset and gain compensation

A novel fully differential track-and-hold stage is proposed. The gain of the stage does not depend on capacitor matching, and it uses a predictive correlated-double-sampling scheme to reduce the effects of op-amp offset and finite dc gain. Due to these properties, it is well suited for the construction of a fully differential sample-and-hold stage using a ping-pong approach. Simulations indicate that the circuit is capable of high-speed and high-accuracy operation without requiring high-quality components. >

Offset- and gain-compensated track-and-hold stages

A class of new fully-differential track-and-hold stages is presented. The gain of the stages does not depend on capacitor matching, and a predictive correlated-double-sampling scheme is used to reduce the effects of op-amp offset and finite dc gain. A prototype chip was fabricated in a 1.2 /spl mu/m double-poly double-metal CMOS process. Measured results indicated that the proposed track-and-hold stage is superior in both speed and accuracy to other commonly used CMOS sample-and-hold stages implemented on the same chip.

A high-linearity low-voltage all-MOSFET delta-sigma modulator

The implementation of a second-order switched-capacitor delta-sigma modulator is described. The modulator uses MOSFETs in their accumulation region as capacitors, with the input branches linearized using series compensation. It utilizes only basic digital CMOS technology and was fabricated in a 1.2 /spl mu/m process. The chip area of the modulator is about 1 mm/sup 2/. Measured results show that the modulator has a 94 dB peak S/THD, a 96 dB peak S/N and an 86 dB peak S/THD+N for a 6 kHz bandwidth with 5.4 mW power dissipation using a 3 V power supply and a 3.6 V capacitor bias voltage.

Experimental results on reduced harmonic distortion in circuits with correlated double sampling

It is shown both by analysis and experiment that in a class of SC circuits using correlated double sampling (CDS), the harmonic distortion caused by nonlinear op-amps is greatly reduced. These circuits are very useful in applications such as input stages in high-linearity amplifiers or in delta-sigma converters, especially in a low-voltage technology.

The realization of delta-sigma A/D converters in low-voltage digital CMOS technology

This paper discusses the design of high-linearity analog CMOS circuits in basic digital CMOS technology, which allows only low supply voltages and has a single polysilicon layer. The key design issues are described, and illustrated with the design details of two delta-sigma ADCs. The first features a very low (1.8 V) supply voltage and a 94 dB dynamic range, while the second one contains only MOSFETs, no capacitors or resistors, and achieved 94 dB peak S/THD and SNR.

Novel high-frequency track-and-hold stages with offset and gain compensation

Two novel fully-differential track-and-hold stages are proposed. The gain of the stages does not depend on capacitor matching, and they use a predictive correlated-double-sampling scheme to reduce the effects of op-amp offset and finite dc gain. Due to these properties, they are well suited for the construction of a fully-differential sample-and-hold stage using a ping-pong approach. Simulations indicate that these circuits are capable of high-speed and high-accuracy operation without requiring high-quality components.