Reza Meraji

A Receiver Architecture for Devices in Wireless Body Area Networks

A receiver architecture suitable for devices in wireless body area networks is presented. Such devices require minimum physical size and power consumption. To achieve this the receiver should, therefore, be fully integrated in state-of-the-art complementary metal-oxide-semiconductor (CMOS) technology, and size and power consumption must be carefully considered at all levels of design. The chosen modulation is frequency shift keying, for which transmitters can be realized with high efficiency and low spurious emissions. A direct-conversion receiver architecture is used to achieve minimum power consumption and a modulation index equal to two is chosen, creating a midchannel notch in the modulated signal. A tailored demodulation structure has been designed to make the digital baseband compact and low power. To increase sensitivity it has been designed to interface with an analog decoder. Implementation in the analog domain minimizes the decoder power consumption. Antenna design and wave propagation are taken into account via simulations with phantoms. The 2.45-GHz ISM band was chosen as a good compromise between antenna size and link loss. An ultra-low power medium access scheme has been designed, which is used both for system evaluation and for assisting system design choices. Receiver blocks have been fabricated in 65-nm CMOS, and a radio-frequency front-end and an analog-to-digital converter have been measured. Simulations of the complete baseband have been performed, investigating impairments due to 1/f noise, frequency and time offsets.

An analog (7,5) convolutional decoder in 65 nm CMOS for low power wireless applications

A complete architecture with transistor level simulation is presented for a low power analog convolutional decoder in 65 nm CMOS. The decoder core operates in the weak inversion (sub-VT) and realizes the BCJR decoding algorithm corresponding to the 4-state tail-biting trellis of a (7,5) convolutional code. The complete decoder also incorporates serial I/O digital interfaces and current mode differential DACs. The simulated bit error rate is presented to illustrate the coding gain compared to an uncoded system. Our results show that a low power, high throughput convolutional decoder up to 1.25 Mb/s can be implemented using analog circuitry with a total power consumption of 84 µW. For low rate applications the decoder consumes only 47 µW at a throughput of 250 kb/s.

Transistor sizing for a 4-state current mode analog channel decoder in 65-nm CMOS

Analog decoders are constructed based on interconnecting CMOS Gilbert vector multipliers using transistors operating in the sub-VT region. They are seen as an interesting alternative to digital implementations with a low transistor count and a potential for a very low power consumption. Analog implementation makes the circuit sensitive to mismatch, requiring careful transistor sizing. A simulation technique combining Monte-Carlo analysis in Spectre with Matlab processing has therefore been used to investigate transistor sizing for an analog (7,5) convolutional decoder. The simulation results indicate that with a tail-biting trellis circle size 14 with transistor size W/L = 1.0µm/0.6µm, the decoder can offer close to maximum coding gain while operating on very low currents when implemented in 65-nm CMOS technology.

Analog and digital approaches for an energy efficient low complexity channel decoder

This paper presents a study of analog and digital versions of a low complexity channel decoder to investigate the overall performance of both circuits in 65nm CMOS for moderate bit rate applications. Both decoding circuits realize the corresponding decoding algorithm for the convolutional codes generated by the well known 4-state (7,5)8 encoder. The two digital and analog implementations are then analyzed for power consumption, offered coding gain, required silicon area and energy efficiency. The simulations show that the analog circuit outperforms its digital version by a factor of 10X at nominal supply voltage for the same throughputs. Furthermore, the analog implementation is 4.6 times smaller in area than its counterpart.

Low Power Analog and Digital (7,5) Convolutional Decoders in 65 nm CMOS

Targeting emerging energy constrained bio-implantable or wearable wireless devices, this work presents design space exploration of decoding circuits for (7,5)8 convolutional codes in 65 nm CMOS for ultra-low power operation. Decoders operating in digital and analog domains are designed and measured for energy efficiency, bit error rate (BER) performance and throughput. For the analog decoders which are sensitive to noise and device mismatch, the overall effects of transistor dimensions on the output BER are also investigated. The digital implementation with 0.11 mm2 area consumes minimum energy at 0.32 V supply, which gives 9 pJ/b energy efficiency at 125 kb/s and 2.9 dB coding gain. Likewise, in analog domain, three decoding circuits are fabricated that share the same topology and design, except for transistor dimensions. The largest analog decoding core (AD1) takes 0.104 mm2 and the other two (AD2 and AD3) are 0.035 mm2 and 0.015 mm2, respectively. Consequently, coding gain in trade-off with silicon area and throughput is presented. The analog decoders operate with 0.8 V supply, and 2.3 dB coding gain with 10 pico-Joules per bit (pJ/b) energy efficiency is achieved at 2 Mbps.

A low power analog channel decoder for Ultra Portable Devices in 65 nm technology

This paper presents the architecture and the corresponding simulation results for a digitally interfaced ultra-low power extended Hamming decoder implemented in analog integrated circuitry. STs 65nm low power CMOS design library was used to simulate the complete decoder including a serial input digital interface, an analog decoding core and a serial output digital interface. The simulated bit error rate (BER) performance of the decoder is presented and compared to the ideal performance of the Hamming code. Transistor-level simulation results show that an ultra low power, high throughput Hamming decoder up to 2.5 Mb/s can be implemented using analog circuitry working in sub-threshold (sub-VT ) region with a total power consumption below 40 µW. The decoder consumes less than 16 µW when a lower throughput of 250 kb/s is desired.