Ricardo Pires

QoSS hierarchical NoC-based architecture for MPSoC dynamic protection

As electronic systems are pervading our lives, MPSoC (multiprocessor system-on-chip) security is becoming an important requirement. MPSoCs are able to support multiple applications on the same chip. The challenge is to provide MPSoC security that makes possible a trustworthy system that meets the performance and security requirements of all the applications. The network-on-chip (NoC) can be used to efficiently incorporate security. Our work proposes the implementation of QoSS (quality of security service) to overcome present MPSoC vulnerabilities. QoSS is a novel concept for data protection that introduces security as a dimension of QoS. QoSS takes advantage of the NoC wide system visibility and critical role in enabling system operation, exploiting the NoC components to detect and prevent a wide range of attacks. In this paper, we present the implementation of a layered dynamic security NoC architecture that integrates agile and dynamic security firewalls in order to detect attacks based on different security rules. We evaluate the effectiveness of our approach over several MPSoCs scenarios and estimate their impact on the overall performance. We show that our architecture can perform a fast detection of a wide range of attacks and a fast configuration of different security policies for several MPSoC applications.

Dynamic NoC-based architecture for MPSoC security implementation

MPSoCs have been proposed as a promising architecture choice to overcome the challenging embedded electronics requirements, characterized by tights development times and fast evolution of applications. The MPSoC flexibility, also represents a system vulnerability. As security requirements vary dramatically for different applications, the challenge is to provide MPSoC security that allows a trustworthy system that meets all the security requirements of such applications. NoC has become an attractive alternative to support the MPSoC communication requirements. Our work proposes the implementation of dynamic security architecture to overcome present MPSoC vulnerabilities. We integrate agile and dynamic security firewalls into the NoC in order to detect attacks based on different security rules. We evaluate the effectiveness of our approach over several MPSoCs scenarios and estimate their impact on the overall performance. We show that our architecture can perform a fast detection of a wide range of attacks and a fast configuration of the different security policies for several MPSoC applications.

Security-enhanced 3D communication structure for dynamic 3D-MPSoCs protection

Three-dimension Multiprocessors System-on-Chip (3D-MPSoCs) hold promises to allow the development of compact and efficient devices. By means of such technology, multiple applications are supported on the same chip, which can be mapped dynamically during the execution time. This flexibility offered by the 3D technology, also represents vulnerability, turning the 3D-MPSoC security into a challenging task. 3D communication structures (3D-HoCs), which combine buses and network-on-chip can be used to efficiently overcome the present 3D-MPSoC vulnerabilities. 3D-HoCs can be used to implement different security services, monitor the data exchange and isolate dangerous IPs. In this paper, we implement Quality of Security Service (QoSS) in 3D-HoC to efficiently detect and prevent attacks by means of agile and dynamic security firewalls. Such a method takes advantage of the 3D-HoC wide system visibility and critical role in enabling system operation. We evaluate the effectiveness of our approach over several 3D-MPSoCs attack scenarios and estimate their impact on the overall performance. Results show that our architecture can perform a fast detection of a wide range of attacks and a fast configuration of the different security policies.

Implementation of QoSS (quality-of-security service) for NoC-based SoC protection

Many of the current electronic systems embedded in a SoC (System-on- Chip) are used to capture, store, manipulate and access critical data, as well as to perform other key functions. In such a scenario, security is considered as an important issue. The Network-on-chip (NoC), as the foreseen communication structure of next-generation SoC devices, can be used to efficiently incorporate security. Our work proposes the implementation of QoSS (Quality of Security Service) to overcome present SoC vulnerabilities. QoSS is a novel concept for data protection that introduces security as a dimension of QoS. In this paper, we present the implementation of two security services (access control and authentication), that may be configured to assume one from several possible levels, the implementation of a technique to avoid denial-of-service (DoS) attacks, evaluate their effectiveness and estimate their impact on NoC performance.

Hierarchical NoC-based security for MP-SoC dynamic protection

MPSoCs are able to support multiple applications on the same chip. This flexibility offered by the MPSoC also represents a vulnerability, turning the MPSoC security specially challenging. The goal of the designers is to provide MPSoC protection that meets the performance and security requirements of all the applications. The Network-on-chip (NoC) interconnection structure can be used to efficiently overcome the present MPSoC vulnerabilities. In this paper, we present the implementation of a hierarchical security NoC-based architecture to detect and prevent a wide range of MPSoC attacks. We integrate agile and dynamic security firewalls into the NoC in order to detect attacks based on different security rules. It uses the QoSS (Quality of Security Service) concept. It takes into account the tradeoff between security and performance. We evaluate the effectiveness of our approach over several MPSoCs attack scenarios and estimate their impact on the overall performance. We show that our architecture can perform a fast detection of a wide range of attacks and a fast configuration of the different security policies for several MPSoC applications.

QoS 3D-HoC hybrid-on-chip communication structure for dynamic 3D-MPSoCs

Three dimension Multi processors System-on-Chip (3D-MPSoCs) hold promises to allow the development of compact and efficient devices. They support many applications on the same die, able of being mapped dynamically during the execution time. Each application may have different communication requirements. Quality-of-Service (QoS) can be implemented at the communication structure (CS) to support the communication requirements of the dynamic 3D-MPSoC. Our work proposes QoS 3D-HoC, a new 3D-CS that implements the QoS. We evaluate the performance of our architecture over several 3D-MPSoC synthetic and real traffic scenarios and estimate their impact overall CS performance. We compare our architecture against the previous 3D-CS with and without QoS and show that our approach meets the communication requirements while reducing the latency and power up to 87% and 39%, respectively when compared to single 3D-NoC.

Hybrid-on-chip communication architecture for dynamic MP-SoC protection

MPSoCs are able to support multiple applications on the same chip. This flexibility also represents a vulnerability, turning the MPSoC security specially challenging. Most of the current MPSoCs security services are based on symmetric and public-key cryptographic mechanisms. So that, MPSoCs integrate a large set of keys that must be exchanged in an efficient and secure way. In such scenario, any security concept will be ineffective if the key management is weak. In this paper, we present the implementation of an on-chip hybrid communication (HoCs) security-based architecture, that combines bus and Network-on-chip (NoC), to address the efficient and secure key management at MPSoCs. The HoC implements dynamically the QoSS (Quality of Security Service) concept that allows the customization of security. We evaluate the effectiveness of our approach over several MPSoCs attack scenarios and estimate their impact on the overall performance. We show that our architecture can perform a fast detection of a wide range of attacks and a fast configuration of the different security policies for several MPSoC applications. Our hybrid approach saves upto 16% and 25% of communication latency and power consumption, respectively, when compared to the NoC-based architecture without any security.

Multi-objective artificial immune algorithm for security-constrained multi-application NoC mapping

Current SoC (System-on-Chip) are characterized by the integration of larger amount of IPs targeting a wide range of application fields. Such multi-application systems are constrained by a set of security and performance requirements. Network-on-chip (NoC) is becoming important as the communication structure of the SoC. IP mapping is one of the most critical parameters in NoC design, strongly influencing the SoC performance. IP mapping has been solved for single application systems using single and multi-objective optimization algorithms. In this paper we propose the use of a multi-objective adaptive immune algorithm (M2AIA), an evolutionary approach to solve the multi-application NoC mapping problem targeting security issues, in order to group the IPs according the security characteristics while achieving the best performance. Latency and power consumption were adopted as the target multi-objective functions constrained by the security function. To compare the efficiency of our approach, our results are compared with those of the genetic and branch-and-bound multi-objective mapping algorithms. The experimental results showed that the M2AIA achieves configurations that fulfill the security requirements while decreasing the power consumption in 27% and the latency in 42% compared to the branch-and-bound approach and 29% and 36% over the genetic approach.

The LRD traffic impact on the NoC-based SoCs

Designing an optimal NoC for a particular application requires the specification of a large set of configuration parameters leading to a wide solution space. NoC performance highly depends on SoC traffic. NoC traffic has been modeled using poisson models not highly correlated. However, it has been shown that LRD (Long Range Dependence) traffic will be an ubiquous property on an future SoC applications. LRD is a property of stochastic process that has a significant impact on the overall network performance. It strongly influence the network buffer size. Our paper has 2 goals: to show the influence of the LRD on the NoC performance and propose a NoC manager mechanism to detect and handle the LRD traffic. We perform SystemC-TLM simulations and show a LRD impact up to 210% over the NoC latency. Our mechanisms were tested and the results show latency and power improvement up to 87% and 63%, respectively, when compared to a best-effort NoC.

An evolutive approach for designing thermal and performance-aware heterogeneous 3D-NoCs

Three dimensional Multiprocessor System-on-Chip (3D-MPSoC) adoption. It is characterized by the integration of a large amount of hardware components on a single multilayer chip. However, heating is one of the major pitfalls of the 3D-MPSoCs. Three dimensional Network-on-Chip (3D-NoC) is used as the communication structure of 3D-MPSoCs. Its main role in system operation and performance makes the optimal 3D-NoC design a critical task. Final 3D-NoC configuration must fulfill all the application requirements and heating constraints of the system. Topology and mapping are some of the most critical parameters in 3D-NoC design, strongly influencing the 3D-MPSoC performance and cost. 3D-NoC topology and mapping has been solved for single application systems on homogeneous 3D-NoCs using single and multi-objective optimization algorithms. In this paper we use a multi-objective immune algorithm (MIA), to solve the multi-application 3D-NoC topology and mapping problems. Latency and power consumption are adopted as the target multi-objective functions constrained by the heating function. Our strategy has been applied on 8 3D-MPSoC benchmarks. Their final 3D-NoC configurations have up to 73% power and 42% latency enhancement when compared to previous reported results.