Wang Jiang Chau

A multi-objective approach for multi-application NoC mapping

Current SoC design trends are characterized by the integration of larger amount of IPs targeting a wide range of application fields. Such multi-application systems are constrained by a set of requirements. In such scenario network-on-chips (NoC) are becoming more important as the on-chip communication structure. Designing an optimal NoC for satisfying the requirements of each individual application requires the specification of a large set of configuration parameters leading to a wide solution space. It has been shown that IP mapping is one of the most critical parameters in NoC design, strongly influencing the SoC performance. IP mapping has been solved for single application systems. In this paper we propose the use of a multi-objective adaptive immune algorithm (M2AIA), an evolutionary approach to solve the multi-application NoC mapping problem. Latency and power consumption were adopted as the target multi-objective functions. To compare the efficiency of our approach, our results are compared with those of the genetic and branch-and-bound multi-objective mapping algorithms. We tested algorithm on several SoC applications.

QoSS hierarchical NoC-based architecture for MPSoC dynamic protection

As electronic systems are pervading our lives, MPSoC (multiprocessor system-on-chip) security is becoming an important requirement. MPSoCs are able to support multiple applications on the same chip. The challenge is to provide MPSoC security that makes possible a trustworthy system that meets the performance and security requirements of all the applications. The network-on-chip (NoC) can be used to efficiently incorporate security. Our work proposes the implementation of QoSS (quality of security service) to overcome present MPSoC vulnerabilities. QoSS is a novel concept for data protection that introduces security as a dimension of QoS. QoSS takes advantage of the NoC wide system visibility and critical role in enabling system operation, exploiting the NoC components to detect and prevent a wide range of attacks. In this paper, we present the implementation of a layered dynamic security NoC architecture that integrates agile and dynamic security firewalls in order to detect attacks based on different security rules. We evaluate the effectiveness of our approach over several MPSoCs scenarios and estimate their impact on the overall performance. We show that our architecture can perform a fast detection of a wide range of attacks and a fast configuration of different security policies for several MPSoC applications.

Comparing two testbench methods for hierarchical functional verification of a bluetooth baseband adaptor

The continuous improvement on the design methodologies and processes has made possible the creation of huge and very complex digital systems. Design verification is one of the main tasks in the design flow, aiming to certify the system functionality has been accomplished accordingly to the specification. A simulation based technique known as functional verification has been followed by the industry. In recent years, several articles in functional verification have been presented, focusing either on specific design verification experiments or on methods to improve and accelerate coverage reaching. In the first category, the majority of the papers are aimed to processors verification, while communication systems experiences were not such commonly reported. In the second category, different authors have proposed methodologies, which need an extensive and complex work by the verification engineer on tuning the acceleration algorithms to the specific design. In the present paper, we present a functional verification methodology applied to a Bluetooth Baseband adaptor core, described in SystemC RTL. Two techniques are considered, one following the traditional framework of applying random stimuli and checking functional coverage aspects; in the second one, a simple acceleration procedure, based on redundant stimuli filtering, is included. For both solutions, a hierarchical approach is adopted. We present several results comparing both solutions, showing the gain obtained in using the acceleration technique. Additionally, we show how results on a real testbench application environment correlate to the hierarchical verification approach taken.

Formal equivalence checking between high-level and RTL hardware designs

Digital applications complexity makes it harder every day to discover and debug behavioral inconsistencies at register transfer level (RTL). Aiming to bring a solution, several techniques have appeared as alternatives to verify that a circuit description meets the requirements of its corresponding functional specification. Simulation is widely applied due to its convenience to uncover early design bugs, but is far from providing the exhaustiveness acquired through formal methods, for which improved and new tools continue to appear. On the other hand, formal verification can suffer from problems such as state-space explosion or modeling inaccuracy. Then, it is vital to develop new ways to check a design for consistency fast and comprehensively. In this paper, we propose a sequential equivalence checking (SEC) formalism and an algorithm, for use between a specification, written at electronic system level (ESL), and an implementation, written at RTL. Given that equivalence is checked between different levels of abstraction, it is no longer valid to perform SEC on single states, thus, we show a scheme to extract and compare complete sequences of states in order to determine if the design intention, which is described in the ESL specification, is contained and respected by the RTL implementation. The results obtained suggest that our methodology can be applied efficiently on real designs.

Dynamic NoC-based architecture for MPSoC security implementation

MPSoCs have been proposed as a promising architecture choice to overcome the challenging embedded electronics requirements, characterized by tights development times and fast evolution of applications. The MPSoC flexibility, also represents a system vulnerability. As security requirements vary dramatically for different applications, the challenge is to provide MPSoC security that allows a trustworthy system that meets all the security requirements of such applications. NoC has become an attractive alternative to support the MPSoC communication requirements. Our work proposes the implementation of dynamic security architecture to overcome present MPSoC vulnerabilities. We integrate agile and dynamic security firewalls into the NoC in order to detect attacks based on different security rules. We evaluate the effectiveness of our approach over several MPSoCs scenarios and estimate their impact on the overall performance. We show that our architecture can perform a fast detection of a wide range of attacks and a fast configuration of the different security policies for several MPSoC applications.

Security-enhanced 3D communication structure for dynamic 3D-MPSoCs protection

Three-dimension Multiprocessors System-on-Chip (3D-MPSoCs) hold promises to allow the development of compact and efficient devices. By means of such technology, multiple applications are supported on the same chip, which can be mapped dynamically during the execution time. This flexibility offered by the 3D technology, also represents vulnerability, turning the 3D-MPSoC security into a challenging task. 3D communication structures (3D-HoCs), which combine buses and network-on-chip can be used to efficiently overcome the present 3D-MPSoC vulnerabilities. 3D-HoCs can be used to implement different security services, monitor the data exchange and isolate dangerous IPs. In this paper, we implement Quality of Security Service (QoSS) in 3D-HoC to efficiently detect and prevent attacks by means of agile and dynamic security firewalls. Such a method takes advantage of the 3D-HoC wide system visibility and critical role in enabling system operation. We evaluate the effectiveness of our approach over several 3D-MPSoCs attack scenarios and estimate their impact on the overall performance. Results show that our architecture can perform a fast detection of a wide range of attacks and a fast configuration of the different security policies.

A placement tool for a NOC-based dynamically reconfigurable system

In the last years, Field programmable gate-arrays (FPGAs) with partial reconfiguration capabilities have raised interest in the implementation of dynamically reconfigurable systems. It has not become a mainstream activity though, due to the lack of solid design methodologies and associated tools. One of the approaches aimed to free the designer of lower level implementation details is to use structured communication resources to provide the interaction between reconfigurable partitions (modules). The architecture of a network-on-chip (NoC) based dynamically reconfigurable system and a placement tool, which automatically places all of its modules, is presented. The tool takes the partitioned design information and the restrictions imposed by the device family architecture into consideration. The basics of the placement algorithm and a study-case as an example are presented.

Implementation of QoSS (quality-of-security service) for NoC-based SoC protection

Many of the current electronic systems embedded in a SoC (System-on- Chip) are used to capture, store, manipulate and access critical data, as well as to perform other key functions. In such a scenario, security is considered as an important issue. The Network-on-chip (NoC), as the foreseen communication structure of next-generation SoC devices, can be used to efficiently incorporate security. Our work proposes the implementation of QoSS (Quality of Security Service) to overcome present SoC vulnerabilities. QoSS is a novel concept for data protection that introduces security as a dimension of QoS. In this paper, we present the implementation of two security services (access control and authentication), that may be configured to assume one from several possible levels, the implementation of a technique to avoid denial-of-service (DoS) attacks, evaluate their effectiveness and estimate their impact on NoC performance.

The Multiple Pairs SMO: A modified SMO algorithm for the acceleration of the SVM training

The Sequential Minimal Optimization (SMO) algorithm is known to be one of the most efficient solutions for the Support Vector Machine training phase. It solves a quadratic programming (QP) problem by optimizing a set of coefficients whose size is the number of training examples. However, its execution time may be quite long due to its computational complexity: the algorithm executes many calculations per iteration as well as many iterations until a stop criterion is satisfied. Due to its importance, many improvements have been proposed in order to obtain faster solutions. These improvements keep unchanged the SMO basic characteristic: the optimization is always performed on one pair of coefficients per iteration. This paper presents the Multiple Pairs SMO (MP-SMO), a new solution for the SMO algorithm that consists of optimizing more than one pair of coefficients per iteration. We show that this algorithm improves the performance results obtained by other known SMO solutions. Our algorithm presents the following characteristics: a) it uses the previously adopted analytical solution; b) its working set selection heuristic has been adapted from known solutions in order to deal with multiple pairs; c) the monotonic convergence of the algorithm has been demonstrated. We applied our MP-SMO algorithm to a set of known benchmarks. We tested the algorithm optimizing two, three and four pairs per iteration. We always obtained better results than the original one pair SMO algorithm.

A strategy for mapping reconfigurable cores in NoCs

In the last years, Field programmable gate-arrays (FPGAs) with partial reconfiguration capabilities have raised interest in the implementation of dynamically reconfigurable systems (DSRs). For dealing with the issue of communication between reconfigurable and fixed partitions, Networks-on-Chip (NoCs) have gained importance in DSR architectures. The mapping of cores in NoCs aims to find the best topological location onto the NoC, such that the metrics of interest can be greatly optimized. In this paper, the mapping strategy for reconfigurable cores into NoCs is presented and the sensibility in respect to the cost function is evaluated. Results confirm the need for mapping optimization algorithms aimed to reduce both the traffic and power consumption.