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Featured researches published by Richard C. Zelley.


Archive | 1989

Multiprocessor system with centralized initialization, testing and monitoring of the system and providing centralized timing

George J. Barlow; Elmer W. Carroll; James W. Keeley; Wallace A. Martland; Victor M. Morganti; Arthur Peters; Richard C. Zelley


Archive | 1986

Apparatus and method of loading a control store memory of a central subsystem

Richard C. Zelley; Mark J. Kenna; Wallace A. Martland


Archive | 1986

Apparatus for loading and verifying a control store memory of a central subsystem

Chester M. Nibby; Richard C. Zelley; Kenneth E. Bruce; George J. Barlow; James W. Keeley


Archive | 1987

System management apparatus for a multiprocessor system

George J. Barlow; Elmer W. Carroll; James W. Keeley; Wallace A. Martland; Victor M. Morganti; Arthur Peters; Richard C. Zelley


Archive | 1990

Method and apparatus for performing health tests of units of a data processing system

George J. Barlow; Richard C. Zelley; James W. Keeley


Archive | 1991

Data processing system having a bus command generated by one subsystem on behalf of another subsystem

Arthur Peters; Richard C. Zelley; Elmer W. Carroll; George J. Barlow; Chester M. Nibby; James W. Keeley


Archive | 1990

Method for performing quality logic tests on data processing systems by sequentially loading test microinstruction programs and operating microinstruction programs into a single control store

Richard C. Zelley; Elmer W. Carroll


Archive | 1993

APARATO PARA CARGAR Y VERIFICAR UNA MEMORIA DE ALMACENAMIENTO DE CONTROL DE UN SUBSISTEMA CENTRAL.

Chester M. Nibby; Richard C. Zelley; Kenneth E. Bruce; George J. Barlow; James W. Keeley


Archive | 1993

APARATO DE GESTION DE SISTEMA PARA UN SISTEMA MULTIPROCESADOR.

George J. Barlow; Elmer W. Carroll; James W. Keeley; Wallace A. Martland; Victor M. Morganti; Arthur Peters; Richard C. Zelley


Archive | 1987

Einrichtung zum laden und pruefen des mikrobefehlsspeichers eines zentralen subsystems. Means for loading and testing of the micro instruction memory of a central subsystem.

Chester M. Nibby; Richard C. Zelley; Kenneth E. Bruce; George J. Barlow; James W. Keeley

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