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Dive into the research topics where Richard G. Bahr is active.

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Featured researches published by Richard G. Bahr.


COMPCON Spring '91 Digest of Papers | 1991

The DN 10000TX: a new high-performance PRISM processor

Richard G. Bahr; Stephen J. Ciavaglia; Barry J. Flahive; Mark Kline; Paul Mageau; Donovan Nickel

The Hewlett-Packard DN 10000TX scales the original DN 10000 processor design to twice the performance through the use of more aggressive semiconductor technologies. The original eleven VLSI chip CPU design has been recast onto eight VLSI chips including a 1.0- mu m structured-custom chip, five submicron gate arrays, and one bipolar floating-point chip. Continuing to exploit the PRISM architecture to achieve multiple operations per cycle, the 36.36 MHz operation provides performance comparable to that of much higher frequency processors. The authors review the DN 10000 product family, and then present in some detail the goals, design approach, and processor implementation of the DN 10000TX.<<ETX>>


Archive | 1988

Method and apparatus for bus lock during atomic computer operations

Bernard Stumpf; George M. Stabler; Richard G. Bahr; Stephen J. Ciavaglia; Barry J. Flahive; Hugh C. Lauer


Archive | 1988

Data processing system for concurrent dispatch of instructions to multiple functional units

John S. Yates; Stephen J. Ciavaglia; John Manton; Michael Kahaiyan; Richard G. Bahr; Barry J. Flahive


Archive | 1992

Duplicate tag store purge queue

Andrew Milia; Richard G. Bahr


Archive | 1990

Multiprocessor bus locking system with a winning processor broadcasting an ownership signal causing all processors to halt their requests

Richard G. Bahr; Andrew Milia; Barry J. Flahive


Archive | 1989

Method and apparatus for concurrent dispatch of instructions to multiple functional units

John S. Yates; John Manton; Richard G. Bahr; Stephen J. Ciavaglia; Michael Kahaiyan; Barry J. Flahive


Archive | 1988

Quasi-fair arbitration scheme with default owner speedup

Andrew Milia; Richard G. Bahr


Archive | 1990

Pipeline computer system having write order preservation

Bernard Stumpf; Mark Kline; Jeffrey D. Kurtze; Richard G. Bahr


Archive | 1990

Apparatus for selective execution of instructions following a branch instruction

Richard G. Bahr; Stephen J. Ciavaglia; John S. Yates; Hugh C. Lauer; Peter Oppen


Archive | 1989

Method and device for simultaneously dispatching instruction to multi-functional unit

Richard G. Bahr; Stephen J. Ciavaglia; Barry J. Flahive; Michael Kahaiyan; John Manton; Jr John S Yates

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Hugh C. Lauer

Mitsubishi Electric Research Laboratories

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