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Dive into the research topics where Barry J. Flahive is active.

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Featured researches published by Barry J. Flahive.


COMPCON Spring '91 Digest of Papers | 1991

The DN 10000TX: a new high-performance PRISM processor

Richard G. Bahr; Stephen J. Ciavaglia; Barry J. Flahive; Mark Kline; Paul Mageau; Donovan Nickel

The Hewlett-Packard DN 10000TX scales the original DN 10000 processor design to twice the performance through the use of more aggressive semiconductor technologies. The original eleven VLSI chip CPU design has been recast onto eight VLSI chips including a 1.0- mu m structured-custom chip, five submicron gate arrays, and one bipolar floating-point chip. Continuing to exploit the PRISM architecture to achieve multiple operations per cycle, the 36.36 MHz operation provides performance comparable to that of much higher frequency processors. The authors review the DN 10000 product family, and then present in some detail the goals, design approach, and processor implementation of the DN 10000TX.<<ETX>>


Archive | 1988

Method and apparatus for bus lock during atomic computer operations

Bernard Stumpf; George M. Stabler; Richard G. Bahr; Stephen J. Ciavaglia; Barry J. Flahive; Hugh C. Lauer


Archive | 1988

Data processing system for concurrent dispatch of instructions to multiple functional units

John S. Yates; Stephen J. Ciavaglia; John Manton; Michael Kahaiyan; Richard G. Bahr; Barry J. Flahive


Archive | 1990

Multiprocessor bus locking system with a winning processor broadcasting an ownership signal causing all processors to halt their requests

Richard G. Bahr; Andrew Milia; Barry J. Flahive


Archive | 1995

Computer apparatus having special instructions to force ordered load and store operations

Dale C. Morris; Barry J. Flahive; Michael L. Ziegler; Jerome C. Huck; Stephen G. Burger; Rugby B.L. Lee; Bernard Stumpf; Jeff Kurtze


Archive | 1989

Method and apparatus for concurrent dispatch of instructions to multiple functional units

John S. Yates; John Manton; Richard G. Bahr; Stephen J. Ciavaglia; Michael Kahaiyan; Barry J. Flahive


Archive | 1997

Computer that selectively forces ordered execution of store and load operations between a CPU and a shared memory

Dale C. Morris; Bernard Stumpf; Barry J. Flahive; Jeffrey D. Kurtze; Stephen G. Burger; Ruby B. Lee; William R. Bryg


architectural support for programming languages and operating systems | 1992

Proceedings of the fifth international conference on Architectural support for programming languages and operating systems

Barry J. Flahive; Richard L. Wexelblat


Archive | 1994

A computer apparatus having a means to force sequential instruction execution

Dale C. Morris; Barry J. Flahive; Stephen G. Burger; Ruby B. Lee; William R. Bryg; Bernard Stumpf; Jeff Kurtze


Archive | 1994

Rechnervorrichtung mit Mitteln zum Erzwingen der Ausführung von Befehlen in regelmässiger Folge Computing device having means for forcing the execution of instructions in a regular sequence

Dale C. Morris; Barry J. Flahive; Stephen G. Burger; Ruby B. Lee; William R. Bryg; Bernard Stumpf; Jeff Kurtze

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