Stephen J. Ciavaglia
Hewlett-Packard
Network
Latest external collaboration on country level. Dive into details by clicking on the dots.
Publication
Featured researches published by Stephen J. Ciavaglia.
COMPCON Spring '91 Digest of Papers | 1991
Richard G. Bahr; Stephen J. Ciavaglia; Barry J. Flahive; Mark Kline; Paul Mageau; Donovan Nickel
The Hewlett-Packard DN 10000TX scales the original DN 10000 processor design to twice the performance through the use of more aggressive semiconductor technologies. The original eleven VLSI chip CPU design has been recast onto eight VLSI chips including a 1.0- mu m structured-custom chip, five submicron gate arrays, and one bipolar floating-point chip. Continuing to exploit the PRISM architecture to achieve multiple operations per cycle, the 36.36 MHz operation provides performance comparable to that of much higher frequency processors. The authors review the DN 10000 product family, and then present in some detail the goals, design approach, and processor implementation of the DN 10000TX.<<ETX>>
Archive | 1988
Bernard Stumpf; George M. Stabler; Richard G. Bahr; Stephen J. Ciavaglia; Barry J. Flahive; Hugh C. Lauer
Archive | 1988
John S. Yates; Stephen J. Ciavaglia; John Manton; Michael Kahaiyan; Richard G. Bahr; Barry J. Flahive
Archive | 1991
Russell Gray Barbour; Carl A. Soeder; Stephen J. Ciavaglia
Archive | 1989
John S. Yates; John Manton; Richard G. Bahr; Stephen J. Ciavaglia; Michael Kahaiyan; Barry J. Flahive
Archive | 1989
Russell Gray Barbour; Carl A. Soeder; Stephen J. Ciavaglia
Archive | 1988
John S. Yates; Stephen J. Ciavaglia
Archive | 1990
Richard G. Bahr; Stephen J. Ciavaglia; John S. Yates; Hugh C. Lauer; Peter Oppen
Archive | 1989
Russell Gray Barbour; A Soeder Carl; Stephen J. Ciavaglia
Archive | 1989
Richard G. Bahr; Stephen J. Ciavaglia; Barry J. Flahive; Michael Kahaiyan; John Manton; Jr John S Yates