Richard W. Jarvis

Product wafer yield prediction method employing a unit cell approach

Split manufacturing method for advanced semiconductor circuits

Multipurpose defect test structure with switchable voltage contrast capability and method of use

Drop-in test structure and methodology for characterizing an integrated circuit process flow and topography

Integrated defect monitor structures for conductive features on a semiconductor topography and method of use

Semiconductor test structure with intentional partial defects and method of use

Test structure and methodology for characterizing etching in an integrated circuit fabrication process

Drop-in test structure and abbreviated integrated circuit process flow for characterizing production integrated circuit process flow, topography, and equipment

Micro-void detection

Test structure and methodology for characterizing ion implantation in an integrated circuit fabrication process