Charles E. May

Semiconductor device having metal gate electrode and titanium or tantalum nitride gate dielectric barrier layer and process of fabrication thereof

Method and test structure for low-temperature integration of high dielectric constant gate dielectrics into self-aligned semiconductor devices

Ultrathin, nitrogen-containing MOSFET sidewall spacers using low-temperature semiconductor fabrication process

Process for formation of isolation trenches with high-K gate dielectrics

Method of making a high performance transistor with elevated spacer formation and self-aligned channel regions

Ion beam milling to generate custom reticles

Trench isolation structure partially bound between a pair of low K dielectric structures

Trench isolation structure having low K dielectric spacers arranged upon an oxide liner incorporated with nitrogen

Method of making N-channel and P-channel IGFETs with different gate thicknesses and spacer widths

Method of making air gap isolation by making a lateral EPI bridge for low K isolation advanced CMOS fabrication