John L. Nistler

Phase shifting and optical proximity corrections to improve CD control on logic devices in manufacturing for sub-0.35-um i-line

The use of I-Line exposure wavelength for manufacturing at and beyond 0.35 micrometers presents many challenges in manufacturing. The lack of resolution, depth of focus, exposure latitude, and iso/dense offsets have caused some to switch from I-Line to DUV. With our installed I-Line base we felt it necessary to implement techniques to extend our tool life, reduce manufacturing costs while improving manufacturing margins. The results of the differential modification techniques were used to reduce the effects of topography, density, and low k lens issues. The differences seen between the binary and phase shift plates show the advantage of phase shifting below 0.35 (mu) manufacturing. We have been able to demonstrate between critical dimension (CD) control using phase shift mask with dense iso compensation over a standard binary reticle. The data shows improved CD control across the stepper field, wafer, and overall lot distribution. The impact of this work was improved speed performance. It also allowed us to move the CDs to smaller dimension because of the better control without increasing fallout due to electrical parametric roll-off.

Large-area optical design rule checker for logic PSM application

An aerial optical design rule checker (ODRC) that will handle large areas is used to validate the automatic CAD software used for application of alternating Phase Shift Mask technology to logic devices. An automatic alternating aperture layout algorithm developed internally by Advanced Micro Devices is applied to 0.24 to 0.50 micrometers electrical designs. The layout is then verified for different stepper and defocus values by the ODRC which utilizes the simulated aerial image to compare directly to the electrical design database. Entire databases are handled by fracturing the database into optically isolated areas or by using a sliding window technique. Small areas up to 420 um per side can be done with single processor workstations with at least 512 megabyte of memory. Larger problems require multiprocessor computers with at least 16 gigabyte of memory. Full circuit analysis should be done on systems with at least 64 gigabyte of memory in order to accomplish solving the problem in a reasonable time frame.

Issues associated with the commercialization of phase-shift masks

Issues associated with the commercialization of phase shift masks are discussed. Design layouts incorporating multiphase transitions and voting are presented along with methods of mask fabrication. Issues associated with mask inspection and repair are discussed, along with data on actual reticles produced using the prescribed method of manufacture. Cost of reticles in relation to potential wafer processing gains are compared along with problems associated with the increased complexity of the mask making process.

Metrology issues associated with submicron linewidths

The three conventional techniques--optical, low voltage scanning electron microscopy (LVSEM), and electrical linewidth measurement--continue to be employed, but each technique has unique applications, problems, and limitations. In this paper these techniques are investigated for submicron linewidth metrology. A great deal of emphasis is placed on the calibration of these tools and the potential for problems associated with the tools.

Phase-shift mask technology: requirements for e-beam mask lithography

Phase-shifted patterns (alternating, 90-degree, and chromeless) have been incorporated into a reticle layout, fabricated with a MEBESR III system, and evaluated experimentally at 365 nm using steppers with numerical aperture (NA) ranging from 0.4 to 0.48 and partial coherence ranging from 0.38 to 0.62. Test circuit layouts simulate actual circuit designs with critical dimensions ranging from 0.2 micrometers to 1.2 micrometers . These results, combined with experimental measurement of layer to layer registration and aerial image simulations, provide a first-order assessment of e-beam lithography requirements to support phase-shift mask technology.

In the year 2525, if x ray is still alive, if lithography can survive, they may find...

Data and discussions will be presented on the NTRM, National Technology Roadmap, for reticles based on a Process Integration perception. Specifically two layers are considered for this paper, the gate layer which is primarily a chrome geometry mask with a lot of open glass and a local interconnect layer which is primarily a chrome plate using clear geometries. Information from other sources is used where appropriate and actual in-house data is used to illustrate specific points. Realizing that demands from different customers for specific types of features tend to drive specific mask makers and their decisions on equipment purchases and processes. We attempt to help predict where Integration approaches have either caused a lag in technology pushes or have actually speeded up certain requirements. Discussions of integration requirements, which tend to push maskmakers, will be presented. Along with typical design approaches in OPC and PSM which either will push technology or actually slow down the trend towards smaller geometries. In addition, data will be presented showing how specific stepper characteristics may actually drive the customers criteria, thus changing the requirements from customer to customer.

Device performance and optimization for 5th- and 6th-generation microprocessors

A family of CMOS processing technologies used to produce AMDs fifth and sixth generation microprocessors (K5 and K6) is described. Some of the issues that arose during the technology development and the transfer to manufacturing are also presented. Transistor performance is compared to literature results and shown to be best in its class.

Detection of submicron phase defects on multiphase random logic reticles

In this paper we present results of an algorithm that has been developed which is sensitive to phase defects of 60 degrees on i-line alternating PSMs. This algorithm consists of microcode and software which can be loaded into existing inspection hardware. The algorithm works in die-to-die inspection mode and uses both transmitted and reflected light images to maximize sensitivity. Isolated phase defects missing and misaligned shifter edges. A programmed phase defect test plate was developed to characterize defect detection sensitivity. Detection of 60 degree defects smaller than 0.75 micrometer has been demonstrated with this algorithm. Defect sensitivity characterization and actual production plate defect results are shown.

Reticle variation influence on manufacturing line and wafer device performance

Cost effective manufacturing of devices at 0.5, 0.35 and 0.25μm geometries will be highly dependent on a companys’ ability to obtain an economic return on investment. The high capital investment in equipment and facilities, not to mention the related chemical and wafer costs, for producing 200mm silicon wafers requires aspects of wafer processing to be tightly controlled. Reduction in errors and enhanced yield management requires early correction or avoidance of reticle problems. It is becoming increasingly important to recognize and track all pertinent factors impacting both the technical and financial viability of a wafer manufacturing fabrication area. Reticle related effects on wafer manufacturing can be costly and affect the total quality perceived by the device customer.