Marie Denison

Moving current filaments in integrated DMOS transistors under short-duration current stress

Integrated vertical DMOS transistors of a 90-V smart power technology are studied under short-duration current pulses. Movement of current filaments and multiple hot spots observed by transient interferometric mapping under nondestructive snap-back conditions are reported. Device simulations show that the base push-out region associated with the filament can move from cell to cell along the drain buried layer due to the decrease of the avalanche generation rates by increasing temperature. The influence of the termination layout of the source field on the hot-spot dynamics is studied. Conditions for filament motion are discussed. The described mechanisms help homogenizing the time averaged current-density distribution and enhance the device robustness against electrostatic discharges.

Measurement and modeling of the electron impact-ionization coefficient in silicon up to very high temperatures

In this paper, an experimental investigation on high-temperature electron impact-ionization in silicon is carried out with the aim of improving the qualitative and quantitative understanding of carrier transport under electrostatic discharge (ESD) conditions. Special test devices were designed and manufactured using Infineons SPT5 technology, namely: a bipolar junction transistor (BJT), a static-induction transistor (SIT) and a vertical DMOS transistor (VDMOS), all of them with a cylindrical geometry. The measurements were carried out using a customized measurement setup that allows very high operating temperatures to be reached. A novel extraction methodology allowing for the determination of the impact-ionization coefficient against electric field and lattice temperature has been used. The experiments, carried out up to 773 K, confirm a previous theoretical investigation on impact-ionization, and widely extend the validity range of the compact model here proposed for implementation in device simulation tools. This is especially useful to predict the failure threshold of ESD-protection and power devices.

Key technologies for system-integration in the automotive and Industrial Applications

System integration and high power density of monolithic and multichip designs are the driving force for the progress in power electronic systems. The whole system has to be considered and optimized to meet this target and to keep the overall ruggedness, sensitivity toward electromagnetic interference and long term reliability, Silicon utilization system reliability and power units miniaturization are the key factors. In this paper new technologies, advanced devices concepts and future system aspect for system-integration in the automotive and industrial segments are discussed. In both fields of applications these are huge requirements toward system dynamic characteristic, overload capability, ruggedness behavior and reliability. In the automotive segment technologies working at high operating temperatures are required and in the industrial are high blocking voltage capabilities are needed.

Experimental extraction of the electron impact-ionization coefficient at large operating temperatures

A theoretical and experimental investigation on the electron impact ionization in silicon has been carried out in the temperature range between 300 and 773 K. The impact-ionization model proposed here amply extends the range of simulation tools up to nearly 800 K, which is especially important in order to predict the failure threshold of ESD-protection and power devices.

Analysis and modeling of DMOS FBSOA limited by n-p-n leakage diffusion current

Failure of DMOS self-heated in saturation below the avalanche threshold is usually related to an activation of the parasitic n-p-n transistor. In this work we show that the exponential increase of the leakage diffusion current of the n-p-n is sufficient to cause thermal runaway, even for a slightly reverse body-source bias caused by the internal ballasting source resistance. Adding this current contribution to a basic DMOS compact model allows simulating the thermal limit of large DMOS transistors considered as distributed electrothermal networks. To our knowledge it is the first report of a quantitative DMOS FBSOA model accounting for the instabilities driven by the temperature dependences of both MOS and n-p-n components

Thermal distribution during destructive pulses in ESD protection devices using a single-shot two-dimensional interferometric method

Thermal distribution during single destructive electrostatic discharge (ESD) events is investigated in smart power ESD protection devices using a two-dimensional holographic interferometry technique. The hot spot dynamics and the position of destructive current filaments is correlated with the thermal distribution under the nondestructive conditions and with the failure analysis results.

A new numerical and experimental analysis tool for ESD devices by means of the transient interferometric technique

Two different protection diodes are investigated with electrothermal simulation and transient interferometric thermal-mapping experiments in a new complementary approach. The prediction capability of the simulation tool is validated up to the thermal failure of the p-n junction. The temperature distribution and its dynamics during the application of high-current pulses are studied by comparing the calculated and experimental optical phase shifts: a quantitative agreement both in temporal evolution and space distribution of temperature is obtained up to 1100 K.

Theory and experimental validation of a new analytical model for the position-dependent Hall Voltage in devices with arbitrary aspect ratio

A number of devices, that are under investigation for implementing and calibrating physical models at high operating temperatures and transient high current stress, exhibit geometrical features that do not allow for the application of the standard Hall theory. This makes the outcome of measurements based on the Hall effect unreliable. A more general theory has been developed, that leads to the determination of the Hall voltage as a function of the position along the longitudinal direction of the device channel. Devices with several pairs of Hall probes have been designed and manufactured, and the Hall voltage along their sides has carefully been measured. The experimental results led to a thorough validation of the theory.

Hot spot dynamics in quasivertical DMOS under ESD stress

Quasivertical DMOS transistors in a 90V Smart Power Technology are studied under ElectroStatic Discharge (ESD) stress. Movement of current filaments and multiple hot spots are observed under snap-back conditions. The hot spot dynamics are explained in terms of the movement of a base push-out region across the cell field as a consequence of the temperature dependence of avalanche generation. The described mechanisms help homogenizing the time averaged current density distribution and enhance the device robustness against ESD events.

Thermal distribution during destructive pulses in ESD protection devices using a single-shot, two-dimensional interferometric method

Thermal distribution during single destructive electrostatic discharge (ESD) events is investigated in smart power ESD protection devices using a novel two-dimensional holographic interferometry technique. The hot spot dynamics and position of destructive current filaments is correlated with the thermal distribution under the non-destructive conditions and with the failure analysis results.