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Dive into the research topics where Ricky C. Hetherington is active.

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Featured researches published by Ricky C. Hetherington.


ieee computer society international conference | 1990

Micro-architecture of the VAX 9000

John E. Murray; Ronald M. Salett; Ricky C. Hetherington; Francis X. Mckeen

The VAX 9000 CPU, a high-performance scalar processor with an integrated vector facility, is discussed. The implementation of the macropipeline found in the four major subsystems of the VAX 9000 is highlighted. The subsystems are the instruction fetch and decode unit (IBOX), the execution unit (EBOX), the data cache and main memory interface (MBOX), and the vector processing unit (VBOX). IBOX combines a 1-cycle access virtual instruction cache with a 25-B instruction buffer and an instruction decode crossbar. The VAX 9000 EBOX performs all scalar operations. It is a pipelined design incorporating a microsequencer to control functional unit operation. The MBOX of the VAX 9000 is the primary source of memory data, and so it is the home of the actual address translation buffer and the data cache. It is multiported and pipelined with two autonomous pipeline segments. The VBOX is an optional arithmetic unit which accelerates arithmetic-intensive code applications.<<ETX>>


Archive | 1991

Scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor system

Michael E. Flynn; Scott Arnold; Stephen J. Delahunt; Tryggve Fossum; Ricky C. Hetherington; David J. Webb


Archive | 1988

Method and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements

Tryggve Fossum; Ricky C. Hetherington; David B. Fite; Dwight P. Manley; Francis X. Mckeen; John E. Murray


Archive | 1989

METHOD AND APPARATUS FOR RESOLVING A VARIABLE NUMBER OF POTENTIAL MEMORY ACCESS CONFLICTS IN A PIPELINED COMPUTER SYSTEM

David B. Fite; Tryggve Fossum; Ricky C. Hetherington; John E. Murray; Jr David A Webb


Archive | 2000

Performance optimization and system bus duty cycle reduction by I/O bridge partial cache line write

Samuel H. Duncan; Glenn Arthur Herdeg; Ricky C. Hetherington; Craig Durand Keefer; Maurice B. Steinman; Paul Michael Guglielmi


Archive | 1993

Integrated circuit chip having primary and secondary random access memories for a hierarchical cache

Ricky C. Hetherington; Francis X. McKeen; Joseph D Marci; Tryggve Fossum; Joel S. Emer


Archive | 1989

Method and apparatus for detecting and correcting errors in a pipelined computer system

Richard C Beaven; Michael B Evans; Tryggve Fossum; Ricky C. Hetherington; William R. Grundmann; John E. Murray; Ronald M. Salett


Archive | 1989

Write back buffer with error correcting capabilities

Ricky C. Hetherington; Tryggve Fossum; Maurice B. Steinman; David A. Webb


Archive | 1989

System for delaying processing of memory access exceptions until the execution stage of an instruction pipeline of a virtual memory system based digital computer

David A. Webb; David B. Fite; Ricky C. Hetherington; Francis X. Mckeen; Mark A. Firstenberg; John E. Murray; Dwight P. Manley; Ronald M. Salett; Tryggve Fossum


Archive | 1989

Instruction buffer system for a digital computer

David B. Fite; Ricky C. Hetherington; Michael M. Mckeon; Dwight P. Manley; John E. Murray

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