Rikky Muller

A 0.013

We present an area-efficient neural signal-acquisition system that uses a digitally intensive architecture to reduce system area and enable operation from a 0.5 V supply. The architecture replaces ac coupling capacitors and analog filters with a dual mixed-signal servo loop, which allows simultaneous digitization of the action and local field potentials. A noise-efficient DAC topology and an compact, boxcar sampling ADC are used to cancel input offset and prevent noise folding while enabling “per-pixel” digitization, alleviating system-level complexity. Implemented in a 65 nm CMOS process, the prototype occupies 0.013 mm2 while consuming 5 μW and achieving 4.9 μVrms of input-referred noise in a 10 kHz bandwidth.

{\hbox {mm}}^{2}

Emerging applications in brain-machine interface systems require high-resolution, chronic multisite cortical recordings, which cannot be obtained with existing technologies due to high power consumption, high invasiveness, or inability to transmit data wirelessly. In this paper, we describe a microsystem based on electrocorticography (ECoG) that overcomes these difficulties, enabling chronic recording and wireless transmission of neural signals from the surface of the cerebral cortex. The device is comprised of a highly flexible, high-density, polymer-based 64-channel electrode array and a flexible antenna, bonded to 2.4 mm × 2.4 mm CMOS integrated circuit (IC) that performs 64-channel acquisition, wireless power and data transmission. The IC digitizes the signal from each electrode at 1 kS/s with 1.2 μV input referred noise, and transmits the serialized data using a 1 Mb/s backscattering modulator. A dual-mode power-receiving rectifier reduces data-dependent supply ripple, enabling the integration of small decoupling capacitors on chip and eliminating the need for external components. Design techniques in the wireless and baseband circuits result in over 16× reduction in die area with a simultaneous 3× improvement in power efficiency over the state of the art. The IC consumes 225 μW and can be powered by an external reader transmitting 12 mW at 300 MHz, which is over 3× lower than IEEE and FCC regulations.

, 5

Recent success in brain-machine interfaces has provided hope for patients with spinal-cord injuries, Parkinsons disease, and other debilitating neurological conditions [1], and has boosted interest in electronic recording of cortical signals. State-of-the-art recording solutions [2–5] rely heavily on analog techniques at relatively high supply voltages to perform signal conditioning and filtering, leading to large silicon area and limited programmability. We present a neural interface in 65nm CMOS and operating at a 0.5V supply that obtains performance comparable or superior to state-of-the-art systems in a silicon area over 3× smaller. These results are achieved by using a scalable architecture that avoids on-chip passives and takes advantage of high-density logic. The use of 65nm CMOS eases integration with low-power digital systems, while the low supply voltage makes the design more compatible with wireless powering schemes [6].

\mu\hbox{W}

This letter presents a monolithic integration of an antenna with an array of neural recording electrodes on a flexible thin film. The structure was designed for long-term neural recording in a wireless brain-machine interface system. The implant-on-body antenna pair is optimized for maximal link power efficiency to maximize the battery life of a portable outside-body control unit. We provide guidelines for the design of the sub-skin-depth implant antenna and validate the antenna simulation model with wireless link measurements in air. We propose a new computational analysis of both the power and voltage delivery to the battery-free implant under design variations to guarantee efficient on-chip RF-to-dc conversion.

, DC-Coupled Neural Signal Acquisition IC With 0.5 V Supply

Substantial improvements in neural-implant longevity are needed to transition brain-machine interface (BMI) systems from research labs to clinical practice. While action potential (AP) recording through penetrating electrode arrays offers the highest spatial resolution, it comes at the price of tissue scarring, resulting in signal degradation over the course of several months [1]. Electrocorticography (ECoG) is an electrophysiological technique where electrical potentials are recorded from the surface of the cerebral cortex, reducing cortical scarring. However, todays clinical ECoG implants are large, have low spatial resolution (0.4 to 1cm) and offer only wired operation.

A Minimally Invasive 64-Channel Wireless μECoG Implant

We present a design methodology for implantable antennas patterned on a flexible substrate for electrocorticography. The antennas are designed for maximum link gain across the human skull to efficiently power the implant. Simulation results show that optimizing the transmission frequency together with antenna geometries can provide sufficient power and voltage to the implant.

A 0.013mm 2 5μW DC-coupled neural signal acquisition IC with 0.5V supply

This review focuses on recent directions stemming from work by the authors and collaborators in the emerging field of neurotechnology. Neurotechnology has the potential to provide a greater understanding of the structure and function of the complex neural circuits in the brain, as well as impacting the field of brain-machine interfaces (BMI). We envision ultralow-power wireless neural interface systems that are life-lasting, fully integrated, and that supports bidirectional data flow with high bandwidth. Moreover, we believe in the importance of building neural interface technology that is truly tetherless, has a very small recording footprint, and little to no mechanical coupling between the sensor and the external world. We believe these developments will impact both neuroscience and neurology, revealing fundamental insight about how the nervous system functions in health and disease.

Design of Wireless Links to Implanted Brain–Machine Interface Microelectronic Systems

This paper presents a high-speed display driver system fabricated in a standard 0.35 mum CMOS technology that operates from a single 3V battery for a 3.0-in. QVGA (320 times RGB times 240) panel. A new amplifier topology, which provides a slew current 100 times the quiescent current, is discussed. The DAC architecture uses COM as a reference to improve the pixel DC accuracy between different panels.

24.1 A miniaturized 64-channel 225μW wireless electrocorticographic neural sensor

A distributed, modular, intelligent, and efficient neuromodulation device, called OMNI, is presented. It supports closed-loop recording and stimulation on 256 channels from up to 4 physically distinct neuromodulation modules placed in any configuration around the brain, hence offering the capability of addressing neural disorders that are presented at the network level. The specific focus of this paper is the communication and power distribution network that enables the modular and distributed nature of the device.

Antenna design for wireless electrocorticography

We present a method for decreasing the duration of artifacts present during intra-cortical microstimulation (ICMS) recordings by using techniques developed for digital communications. We replace the traditional monophasic or biphasic current stimulation pulse with a patterned pulse stream produced by a Zero Forcing Equalizer (ZFE) filter after characterizing the artifact as a communications channel. The results find that using the ZFE stimulus has the potential to reduce artifact width by more than 70%. Considerations for the hardware implementation of the equalizer are presented.