Risho Koh

Buried Layer Engineering to Reduce the Drain-Induced Barrier Lowering of Sub-0.05 µm SOI-MOSFET

The influence of the buried layer structure on the drain-induced barrier lowering (DIBL) is investigated for a silicon-on-insulator metal-oxide-silicon field-effect-transistor (SOI-MOSFET) by a two-dimensional device simulator. The buried layer thickness and the dielectric constant of the buried layer are varied systematically. It is found that the degradation on the threshold voltage can be separated into two components. One component originates from the electric flux via the SOI layer and the other via the buried layer. The buried insulator engineering which controls the thickness and the dielectric constant of the buried layer is effective in reducing the latter component. The gate length limit can be reduced by 23% by the buried air gap structure where the dielectric constant of the buried layer is 1.0.

Capacitance Network Model of the Short Channel Effect for 0.1 µm Fully Depleted SOI MOSFET

We propose a simple analytical model of the short channel effect in a fully depleted silicon-on-insulator metal-oxide-silicon field effect transistor (SOI-MOSFET). The influence of the two-dimensional effect on the potential distribution, the threshold voltage and the S factor are evaluated based on the spatial distribution of the characteristic capacitances between the SOI body and each electrode (gate, source, drain and substrate). This treatment makes it possible to estimate the two-dimensional effect without solving Poissons equation which requires a large computation time. This model describes the short channel effect down to the 0.1 µm regime.

Surface-Enhanced Raman Scattering from Surface Layers of Gas-Evaporated Silver Small Particles

Silver small particles prepared by the gas-evaporation technique with four different heater materials, i.e. Mo, W, C and Ta, have been studied by Raman and X-ray photoemission spectroscopy. Raman spectra of the particles prepared with the Mo and W heaters exhibit a strong and asymmetric band at about 900 cm-1 and a few weak bands below 350 cm-1. These Raman bands are absent in the spectra of particles prepared by C and Ta heaters. Results of XPS suggest the formation of oxides of Mo and W at the particle surfaces. The observed Raman bands can thus be attributed to surface-enhanced bands originating from the oxide coatings. We identify the coatings with amorphous Ag2MoO4 and Ag2WO4.

Simulated Threshold Voltage Adjustment and Drain Current Enhancement in Novel Striped-Gate Nondoped-Channel Fully Depleted SOI-MOSFETs

To enhance the performance of metal-oxide-silicon field-effect-transistors (MOSFETs), a new device having a Silicon-on-insulator (SOI) structure, called a striped-gate SOI-MOSFET, is proposed and its electrical characteristics are estimated by device simulation. The threshold voltage of this device is controlled by changing the length of a metal layer interposed in the gate electrode. A set of systematic device simulations reveals a type of two-dimensional effect in the gate electric field provides a continuous threshold voltage control for a non-doped channel SOI-MOSFET, and that the suppression of the channel doping provides a large drain current. A circuit simulation on a 2-input complementary-MOS (CMOS) NAND gate chain comprising the devices shows that the operation speed is enhanced by 46% compared with that of bulk MOSFETs, due to the devices large drain current and small parasitic capacitance.

Analysis of The Threshold Voltage Adjustment and Floating Body Effect Suppression for 0.1 μm Fully Depleted SOI-MOSFET

The short channel effect for the fully depleted silicon-on-the-insulator metal-oxide-silicon field-effect-transistor (SOI-MOSFET) is analyzed based on a simple analytical model (capacitance network model). It is found that the origin of the short channel effect can be separated into two components. One is the potential modification due to the electric field between the gate electrode and S/D (source and the drain electrode), and the other is the degradation in the vertical component of the electric field of the acceptor. The capacitance network model considering the above two components explains the short channel effect down to the 0.1 µ m regime. The dopant concentration required to adjust threshold voltage is also given by this model. Moreover, based on the above analysis, a new structure to reduce the short channel effect with suppressing the floating body effect is proposed.

An Investigation on the Short Channel Effect for 0.1 µm Fully Depleted SOIMOSFET Using Equivalent One Dimensional Model

An analytical model for the short channel effect for the silicon on insulator metal oxide semiconductor field effect transistor (SOIMOSFET) is proposed. The two dimensional potential problem is reduced to a one dimensional problem, using a virtual electrode which is equivalent to the drain and the source electrodes. The behavior for the short channel effect is also discussed using this model.

Simulation on a Novel Body-Driven Silicon-on-Insulator Metal-Oxide-Silicon Field-Effect-Transistor for Sub-0.1 µm Small Logic Swing Operation

A body-driven silicon-on-insulator metal-oxide-silicon field-effect-transistor (body-driven SOI-MOSFET, BD-MOS) is proposed, and the device characteristics are estimated using a device simulator. This device can remove excess holes within several picoseconds. Additional body contact, which requires additional device area, is not required for removing holes. A small S factor (76 mV/dec.) and a small Vth roll-off (ΔVth=15 mV for ΔVd = 0.4 V) were obtained for the channel length of 0.08 µm, without using very thin gate oxide. An enhancement operation and the large drain current required for complementary-MOS(CMOS)-compatible circuits are achieved.