Ritesh Jhaveri

The Tunnel Source (PNPN) n-MOSFET: A Novel High Performance Transistor

As MOSFET is scaled below 90 nm, many daunting challenges arise. Short-channel effects (SCEs; drain-induced barrier lowering and VTHmiddotrolloff), off-state leakage, parasitic capacitance, and resistance severely limit the performance of these transistors. New device innovations are essential to overcome these difficulties. In this paper, we propose the concept of a novel tunnel source (PNPN) n-MOSFET based on the principle of band-to- band tunneling. It is found that the PNPN n-MOSFET has the potential of steep subthreshold swing and improved Ion in addition to immunities against SCEs. Therefore, such a PNPN n-MOSFET can overcome the ever-degrading on-off characteristics of the deeply scaled conventional MOSFET. The design of the PNPN n-MOSFET was extensively examined using simulations. Devices with source-side tunneling junctions were fabricated on bulk substrates using spike anneal, and the experimental data is presented.

Lifetime of photogenerated carriers in silicon-on-insulator rib waveguides

The lifetime of photogenerated carriers in silicon-on-insulator rib waveguides is studied in connection with the optical loss they produce via nonlinear absorption. We present an analytical model as well as two-dimensional numerical simulation of carrier transport to elucidate the dependence of the carrier density on the geometrical features of the waveguide. The results suggest that effective carrier lifetimes of ⩽1ns can be obtained in submicron waveguides resulting in negligible nonlinear absorption. It is also shown that the lifetime and, hence, carrier density can be further reduced by application of a reverse bias pn junction.

Effect of Pocket Doping and Annealing Schemes on the Source-Pocket Tunnel Field-Effect Transistor

Low operating power is an important concern for sub-45-nm CMOS integrated circuits. Scaling of devices to below 45 nm leads to an increase in active power dissipation (CV2.f) and subthreshold power (IOFF.VDD)Hence, new device innovations are being explored to address these problems. In this paper, we simulate and experimentally investigate the source-pocket tunnel field-effect transistor (TFET), which is based on the principle of band-to-band tunneling, p-i-n and source-pocket TFETs are fabricated with different pocket conditions to observe the effect of the source-side pocket on device performance. Different annealing schemes (spike and conventional rapid thermal annealing) are used to study the effect of annealing conditions on TFET performance. The source-pocket TFET shows a higher ION (~10 times) and steeper subthreshold swing as compared to a p-i-n TFET. The ambipolar conduction is also reduced by using a low-doped drain extension. Low-temperature measurements of the source-pocket TFET were performed, and the subthreshold swing of the source-pocket TFET shows very little temperature dependence, which confirms the dominant source injection mechanism to be band-to-band tunneling.

Asymmetric Schottky Tunneling Source SOI MOSFET Design for Mixed-Mode Applications

Schottky barrier MOSFETs have recently attracted attention as a viable alternative to conventional CMOS transistors for sub-65-nm technology nodes. An asymmetric Schottky tunneling source SOI MOSFET (STS-FET) is proposed in this paper. The Schottky tunneling source SOI MOSFET has the source/drain regions replaced with silicide as opposed to highly doped silicon in conventional devices. The main feature of this device is the concept of a gate-controlled Schottky barrier tunneling at the source. The device was optimized with respect to various parameters such as Schottky barrier height and gate oxide thickness. The optimized device shows excellent short channel immunity, compared to conventional SOI MOSFETs. The asymmetric nature of the device has been shown to improve the leakage current as well as the linear characteristics of the device as compared to conventional Schottky FETs. The STS-FET was fabricated, using conventional processes combined with the present NiSi technology and large angle implantation, and successfully demonstrated. The high immunity to short channel effects improves the scalability, and the output resistance of the device also makes it an attractive candidate for mixed-mode applications.

The effect of traps on the performance of graphene field-effect transistors

This paper studies the performance degradation of graphene field-effect transistors due to the presence of traps. The mobile charge modulation by gate voltage is degraded because of immobile trapped charges. As a result the current is reduced and the on/off ratio is decreased. Extracted mobility using transconductance method is shown to be underestimated considerably due to the effect of traps.

The SiGe heterojunction source PNPN n-MOSFET with SSOI for low power application

A novel device concept, SiGe tunnel source(PNPN) based on the principle of band to band tunneling is reported in this paper. The SiGe source PNPN tunneling FET shows steep sub-threshold swing and higher turn on current than SiGe source PIN tunnel FET. For achieving high turn on current, the SSOI is also investigated in SiGe tunnel source device.

The tunnel source MOSFET: A novel asymmetric device solution for ultra-low power applications

With aggressive MOSFET scaling, short channel effects (DIBL and VTH roll-off), off-state and gate leakage, parasitic capacitance and resistance severely limit the device performance. These, in addition to VDD scaling limitation and high sub-threshold swing (≫60mv/dec) give rise to high IOFF and make power dissipation, both dynamic and static, an enormous challenge, especially for low power/low current applications. New device innovations are essential to achieve low IOFF by having steep sub-threshold behavior for low power applications. Towards this end, a novel asymmetric Tunneling Source MOSFET is proposed in this paper. The main feature of this device is the concept of gate controlled carrier injection through band-to-band tunneling at the source junction. This novel device has the potential for steep sub-threshold behavior (≪60mv/dec), improved ION/IOFF and high ROUT and gain (gm × ROUT) at low bias currents. It also possesses excellent immunity against short channel effects which improves scalability into sub-50nm regime and makes it an attractive candidate for low power digital and analog operations.

Circuit-Level Performance Evaluation of Schottky Tunneling Transistor in Mixed-Signal Applications

Schottky tunneling source FET (STSFET) is a promising device alternative for future nanometer-scale technology. This paper presents a circuit-level performance evaluation of using STSFET for mixed-signal circuit applications, as well as a design approach that can guide circuit designers to use STSFET optimally. A switched-capacitor track-and-hold amplifier is chosen as a test vehicle, and circuit-level power-performance tradeoff is examined when STSFET is incorporated into the existing array of device types in 90-nm CMOS process. To quantitatively explore the design tradeoff, this paper employs an automated circuit optimization framework using geometric programming, a special type of convex optimization problem. Numerical analysis shows that for our test bench circuit, introducing STSFET, when compared to using devices in 90-nm CMOS process, leads to 30%-50% power reduction, depending on the performance specifications. The analysis also reveals that the full benefit of using STSFET can only be achieved by judiciously choosing device types in a given circuit structure, and the optimal device type selection for a mixed-signal circuit can often be blended using both conventional devices and application-specific devices.

Device-circuit co-optimization for mixed-mode circuit design via geometric programming

Modern processing technologies offer a number of types of devices such as high-VT, low-VT, thick-oxide, etc. in addition to the nominal transistor in order to meet system performance and functional needs. While designers have leveraged these devices for mixed-signal design, a design framework is needed to guide designers in selecting the best set of devices. The same framework can enable device manufacturers decide which new devices to include in the suite of device offerings. This paper presents a design methodology that can quickly guide a designer in selecting the best set of devices for a given application, specifications, and circuit structure. The equation-based optimization framework based on geometric programming (GP) extends upon previous efforts that optimize sizing, biasing, and supply voltages. The paper first shows that convex piecewise-linear function fitting can effectively model for optimization all the types of devices offered by a 90 nm CMOS technology. Additionally, we show the potential to model and include experimental devices such as a Schottky tunneling source MOSFET. Second, the paper applies the model to an example circuit, a track-and-hold amplifier. The optimization and subsequent simulation illustrate the importance and amount of benefit from applying device selection.

ASYMMETRIC TUNNELING SOURCE MOSFETS: A NOVEL DEVICE SOLUTION FOR SUB-100NM CMOS TECHNOLOGY

The paper presents a simulation study of the physics and performance of novel asymmetric tunneling solutions for the sub-100nm MOSFET technology. Two device structures have been investigated: Schottky Tunneling Source MOSFET and band-to-band P+-N+ Tunneling Source MOSFET. The Schottky MOSFET exhibits degraded Ion and subthreshold swing (in spite of improved DIBL). On the other hand, the novel PNPN MOSFET shows high Ion/Ioff and steep subthreshold behavior.