Ritesh Joshi

An analytical approach to dynamic crosstalk in coupled interconnects

This paper deals with waveform analysis, crosstalk peak and delay estimation of CMOS gate driven capacitively and inductively coupled interconnects. Simultaneously switching inputs for the coupled interconnects are considered. A transmission line-based coupled model of interconnect is used for analysis. Alpha-power Law model of MOS transistor is used to represent the transistors in CMOS driver. Peaks and delays at far-end of victim line are estimated for conditions when the inputs to the two coupled interconnects are switching in-phase and out-of-phase. The comparison of analytically obtained results with SPICE simulations show that the proposed model captures noise peak and their timing; 90% propagation delay; transition time delay and waveform shape with good accuracy, such as not more than 5% error in crosstalk peak estimation.

Crosstalk analysis and repeater insertion in crosstalk aware coupled VLSI interconnects

Purpose – To analyze factors affecting crosstalk and to study the effect of repeater insertion on crosstalk, power dissipation and propagation delay.Design/methodology/approach – Crosstalk is effected by transition time of the signal; length of interconnect; distance between interconnects; size of driver and receiver; pattern of input; direction of flow of signal; and clock skew. This work is based on simulating interconnects with parameters obtained from 0.13 μm process. The types of noise addressed are overshoot; undershoot and oscillatory noise. Further, to study the effect of repeater insertion on crosstalk, repeaters are inserted in one line, i.e. line A only. Uniform repeaters varying in number from 1 to 60 are each of size Wn=3.9 μm and Wp=7.8 μm. Both lines A and B are terminated by a capacitive load of 5 fF. A crosstalk noise effect is measured for line A loaded with repeaters. The number of repeater is varied for four different cases of stimulations to both lines viz. input to line A, i.e. VA sw...

Effect of line resistance and driver width on crosstalk in coupled VLSI interconnects

– This paper proposes to study the effect of line resistance and driver width on crosstalk noise for a CMOS gate driven inductively and capacitively coupled VLSI interconnects., – The paper considers a distributed RLC interconnect topology. The interconnect length is 4 mm and far‐end capacitive loading is 30 fF. The SPICE simulation set‐up uses an IBM 0.13 μm, 1.2 V technology model. The input falling ramp has a transition time of 50 ps. The victim line is grounded through a driver resistance of 50 Ω at near end of interconnect. While observing the effect of line resistance, the aggressor driver has PMOS and NMOS widths of 70 and 30 μm, respectively, and the line resistance is varied from 0 to 500 Ω. For capturing the effect of driver width, SPICE waveforms are generated at far end of victim line for three different line resistances (R=0, 30, and 60 Ω respectively). In each case, the aggressor PMOS driver width is swept from 20 to 100 μm. The corresponding NMOS width is half of PMOS width., – It is observed that, as line resistance increases, the noise peak reduces. This is due to the fact that with increasing resistance the incident and reflected waves traveling along the line experience increasing attenuation. Hence, the waves arriving at the far‐end of the line are of smaller magnitude and larger time durations. This causes noise pulses in the lossy lines to be smaller and wider compared with those in a lossless line. The effect of driver width on noise waveforms is further observed. It is observed that, as the PMOS (and corresponding NMOS) driver width is increased, the victim line gets more prone to crosstalk noise. The crosstalk magnitude level increases alarmingly as driver width is increased, because the driver resistance decreases, which in turn increases the current driving capability of driver., – While designing coupled interconnects, driver width and line resistance play an important role in deciding the crosstalk level. An interconnect designer often increases driver width and reduces line resistance for achieving lower propagation delays. This effort may result in higher crosstalk noise in coupled interconnect. Therefore, a designer should be concerned simultaneously for crosstalk noise while reducing delays.

Voltage scaling : a novel approach for crosstalk reduction in global VLSI interconnects

Purpose – To analyze the effect of voltage scaling on crosstalk.Design/methodology/approach – Voltage scaling has been often used for reducing power dissipation of CMOS driven interconnects. An undesired effect observed due to voltage scaling is increase in propagation delay. Thus, a trade off lies between power dissipation and propagation delay with voltage scaling. However, voltage scaling can result in overall reduction of power delay product. Therefore, their lies an optimized supply voltage where‐in power dissipation and propagation delay can be optimized. Many of the previous researches have discussed about power dissipation and propagation delay only with voltage scaling. This paper for first time shows the effect on crosstalk in voltage scaled interconnects. In this paper, we primarily study the noise for an input signal having transition time of 50 ps. The simulations are run for interconnect length of 2 and 4 mm. These parameters are varied for four different cases of stimulations to aggressor a...

Waveform Analysis and Delay Prediction in Simultaneously Switching CMOS Gate Driven Inductively and Capacitively Coupled On-Chip Interconnects

This paper focuses on waveform analysis and delay estimation of a CMOS gate driven capacitively and inductively coupled interconnect for simultaneously switching inputs. A transmission line based coupled model of interconnect is used for analysis. Delays at far-end of victim are estimated for the conditions when the inputs to two coupled interconnects are switching in-phase and out-of-phase. Alpha Power Law model of MOS-transistor is used to represent the transistors in CMOS-driver. The comparison of analytically obtained results with SPICE simulations show that the proposed model captures 90% propagation delay; transition time delay and waveform shape with good accuracy.

Gujjar community rehabilitation from Rajaji National Park: moving towards an integrated approach for Asian elephant (Elephas maximus) conservation.

Abstract Rehabilitation of Gujjar community from the Rajaji National Park area is a persistent and better effort in the direction of wildlife conservation in India. On one hand it has provided the better opportunity for livelihood to pastoral Gujjars and on the other hand it has promoted the regeneration of forest wealth along with movement related activities of wildlife. The major objectives of the study are to generate the database of impact of Gujjar rehabilitation on frequent movement of wildlife. Eight forest ranges were surveyed for about seven years before and after the resettlement of Gujjar and all the data on animal sighting, movement and vegetation component were recorded. Currently wild animals are utilizing whole of the forest area frequently for their routine activities whereas before the resettlement of Gujjars wild animals generally used the water points after sunset. The undisturbed conditions created as a result of the resettling of the pastoral Gujjars, have had a noticeable effect on the elephant and tiger population of the forest area. As per the records of 1998 a total of 1390 families were existing in the park area and after the commencement of the programme 512 families were resettled at Pathri area and 613 were relocated at Gaindikhatta area. Presently 265 families are to be relocated who are residing inside the national park area. After the establishment of state Uttarakhand the rehabilitation programme has conducted very rapidly and over the past six years five forest ranges of the park are freed from the Gujjars.

Crosstalk Analysis of Simultaneously Switching Inductively and Capacitively Coupled Interconnects Driven by CMOS Gate

This paper deals in waveform analysis, crosstalk peak and delay estimation of a CMOS gate driven capacitively and inductively coupled interconnect for simultaneously switching inputs. A transmission line based coupled model of interconnect is used for analysis. Peaks and delays at far-end of victim line are estimated for the conditions when the inputs to two coupled interconnects are switching in-phase and out-of-phase. Waveforms are analyzed in general with homogeneous and non-homogeneous drivers for unipolar inputs. Alpha Power Law model of MOS-transistor is used to represent the transistors in CMOS-driver. The comparison of analytically obtained results with SPICE simulations show that the proposed model captures noise peak and their timing; 90% propagation delay; transition time delay and waveform shape with good accuracy.